JPS6375043U - - Google Patents
Info
- Publication number
- JPS6375043U JPS6375043U JP1986170844U JP17084486U JPS6375043U JP S6375043 U JPS6375043 U JP S6375043U JP 1986170844 U JP1986170844 U JP 1986170844U JP 17084486 U JP17084486 U JP 17084486U JP S6375043 U JPS6375043 U JP S6375043U
- Authority
- JP
- Japan
- Prior art keywords
- metal frame
- semiconductor chip
- fixed
- integrated circuit
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000004020 conductor Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図及び第２図はそれぞれ本考案の第１及び
第２の実施例の断面図である。 １……金属フレーム、２……集積回路チツプ、
３……電源用コンデンサ、４……導電材、５，６
，７……ワイヤ、８，９……リード端子、１０…
…封入材、１１……ワイヤ。
第２の実施例の断面図である。 １……金属フレーム、２……集積回路チツプ、
３……電源用コンデンサ、４……導電材、５，６
，７……ワイヤ、８，９……リード端子、１０…
…封入材、１１……ワイヤ。
Claims (1)
- 金属フレームの一方の面に固定される半導体チ
ツプと、前記金属フレームの他方の面に固定され
それぞれの電極が前記半導体チツプの電源端子及
び接地端子に接続される電源用コンデンサとを含
み、それらを一体に形成することを特徴とする集
積回路パツケージ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986170844U JPS6375043U (ja) | 1986-11-05 | 1986-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986170844U JPS6375043U (ja) | 1986-11-05 | 1986-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6375043U true JPS6375043U (ja) | 1988-05-19 |
Family
ID=31105929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986170844U Pending JPS6375043U (ja) | 1986-11-05 | 1986-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6375043U (ja) |
-
1986
- 1986-11-05 JP JP1986170844U patent/JPS6375043U/ja active Pending