JPS6195477A - Vector processing device - Google Patents

Abstract

PURPOSE:To carry out a processing at high speed since an using efficiency of a vector computing element and a data transfer circuit can be enhanced, by dividing one vector instruction into plural vector processing units and processing. CONSTITUTION:Each of vector arithmetic units 4-7 carries out a transfer of a data with a main memory device 1 through plural vector registers 9, one or plural vector computing element 10 and a memory device control unit 2. In this transfer, connection bus selecting circuits 24, 25 forming a data bus between data transfer circuits 11-13, the vector register 9 and the vector computing element 10 or the data transfer circuits 11-13 are included. Also an instruction performing control section 15 controlling an operation of all the vector arithmetic units connected to these elements is included. A scalar arithmetic processing unit 3 carries out a some task and when it has to perform a vector processing on the way thereof, it is done by the vector processing units 4-7 through a vector arithmetic control unit 8.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a vector processing device.

[Background of the invention]

In conventional vector processing devices, in order to increase processing speed,
It has a plurality of data transfer circuits that manage data transfer between vector arithmetic units, main memory, and vector registers.

7')' L. In the vector instructions that constitute actual vector processing, the number of vector instructions that can be executed simultaneously is small, and these multiple vector arithmetic units and data transfer circuits cannot be used at the same time. The purpose of the present invention is to provide a vector processing device that increases the efficiency of use of a vector arithmetic unit and a data transfer circuit and achieves high-speed processing.

[Summary of the invention]

The present invention provides a vector processing device including a plurality of vector registers, a plurality of vector arithmetic units, and a plurality of data transfer circuits.
A plurality of vector arithmetic processing units each including one vector arithmetic unit and at least one data transfer circuit are prepared, and when executing one vector instruction, the number of vector elements to be processed is instructed for each vector arithmetic processing unit, and the overall This makes it possible to perform vector processing for the number of elements that should originally be processed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram showing an embodiment of the vector processing device of the present invention, in which 1 is a main storage unit, 2 is a storage control unit, 5 is a scalar operation processing unit, and 4 to 7 are vector operation units. Processing unit 8 is a vector arithmetic processing unit and a vector arithmetic control unit that controls the operations of 4 to 7. The scalar arithmetic processing unit 6 is equipped with conventional arithmetic processing functions well known in the art. Each of the vector arithmetic processing units 4 to 7 has a plurality of vector registers 9, one or more vector Arithmetic unit 10. Data transfer circuits 11 to 13 that transfer data to and from the main storage device 1 via the storage device control unit 2.
゜Connection path selection circuits 24 and 25 that form a data bus between the vector register 9 and the vector arithmetic unit 10 or the data transfer circuits 11 to 1S, and instructions that are connected to these elements and control the operation of the entire vector arithmetic processing unit. It includes an execution control section 15.

Although the figure shows the vector arithmetic processing unit 4 in detail, the other vector arithmetic processing units 5 to 7 have the same configuration.

Note that data transfer circuits 11 and 12 are for fetching.

The data transfer circuit 15 is for storing. Further, although the connection path selection circuits 24 and 25 are shown to be independent for each vector arithmetic processing unit, they may be connected between all vector arithmetic processing units.

In the system shown in FIG. 1, the scalar arithmetic processing unit 3 is processing a certain task, and in the middle of the process, vector processing must be performed (if this occurs, it is processed by the vector arithmetic processing unit 8 via the vector arithmetic processing unit 8). unit 4
~7 will be processed.

Let us consider a case where the following program is executed by the scalar arithmetic processing unit 3.

DOIQ I=1, 1o.

10 A(1) = B(1) + C(1) In machine language, this is as follows:
element) instruction and three LMA (Load M
multiple Address) instruction and one EX
VP (Execute vector process)
or ) instruction, and the scalar arithmetic processing unit 5
are executed respectively.

LIN INRO, lNR2, lNR4: Command to set constants in increment registers INRo, lNR2) and lNR4 (increment registers are vectored as described later)
prepared inside. ) LMA VARO 2 The start address of matrix A is stored in vector address register V.
Commanded to set it to ARO.

(Vector address register +s is prepared in the vector arithmetic control unit, as will be described later). ) LMA VAR2 The start address of two matrix B is stored in vector address register V.
Command to set it to AR2.

LMA VAR4 The start address of two matrices C is stored in vector address register V.
Commanded to set it on AR4.

EXVP command to do.

Matrices A and B are created by the above LIN and LMA instructions.

Cl (related address control data is set in the vector address register and increment register in the vector arithmetic control unit 8).

Also, the vector instruction string is read out by the EXVP instruction. This vector instruction string is divided into two LVRs (Load Vector register
) instruction and one V E A (Vector ELer
nentwise Add) instruction and one 5TVR (8
It consists of (tore Vector Register) instructions.

LVRVB2. VAR2, 1NR2: Creates the address of the main memory device 1 based on the start address and constant of matrix B set in vector address register VAR2 and increment register NR2, respectively, and outputs data of matrix B one after another from there. and commands to set it in vector register VR2.

Note that the above constant is used as an increment value of the address, and the same applies hereinafter.

LVRVEA, VARa, lNR4: Vector address register VAR4 and increment register lNR4< Create an address in the main memory device 1 based on the set start address and constant of the matrix C, read the data of the matrix C from there, Command to set it in vector register VR4.

VEA VB2. VB2. VEA: Read matrices B and C from vector registers VR2 and 'VR4, respectively, add them together, and store the results in vector register V.
Order R6 to Seratos.

8TVRVB2. VARO, INR.

: Read data from vector register V R67]).

A command is given to write it to an address in the main memory device 1 created based on the start address and constant of the queue operator set in the vector address register VARo and increment register INRo, respectively.

These vector commands are each sent to a vector command buffer 16 within the vector operation control unit 8.

Further, the number of vector processing elements is sent to the vector length register 17 in the vector calculation control unit 8.

FIG. 2 is a block diagram showing details of the vector arithmetic control unit 8 and the data transfer circuit in the vector arithmetic processing unit. The operation of the vector calculation control unit 8 is
This will be explained based on the figure and FIG.

As described above, the instruction execution determination circuit 1B processes the vector instruction buffer 16 into which the vector instruction is input from the scalar operation processing unit 6).

Extract one vector instruction from the first extraction position,
Determine whether it is feasible.

That is, the water replenishment circuit 19 is provided in common to the vector arithmetic processing units 4 to 7, and the vector registers 9. Vector operator 10. One indicator is provided corresponding to each of the data transfer circuits 11 to 15 to indicate whether or not they are in use.

For example, the indicator corresponding to the d vector register V1 is not provided corresponding to each of the vector arithmetic processing units 4 to 7, but only one indicator is provided. The same goes for nine other things.

By referring to these indicators, the command execution determination circuit 18 selects the vector register 9 specified by the retrieved vector instruction and the vector register 9 or the vector register 9 for performing the operation specified by the vector y instruction. Check to see if 10th grade is available, and if you find that all the necessary items are available,
The vector instruction is determined to be executable. In that case, the vector register 9. used in that vector instruction. Vector operator 10. Data transfer circuit 11~
The indicators corresponding to 15 are set to indicate that they are in use, and the vector instruction is sent to the instruction register 20, and at the same time, the start signal 22 is sent to the start control circuit 21.

The vector instruction buffer 16 in FIG. 2 shows the format of one vector instruction sent from the scalar arithmetic processing unit 5.

Further, the instruction register 20 in FIG. 2 shows the format of one vector instruction sent from the instruction execution determination circuit 18.

In this, OF is an operation code representing the type of operation, % VRN1 to 3 are vector register designations i that designate vector registers, VARN is vector address register designation parts that designate vector address registers,
INRN is an increment register designation part that designates an increment register.

Note that some vector instructions do not use a vector address register or the like (for example, the above-mentioned VBA instruction), and in that case, the corresponding specification section does not exist.

For convenience of explanation, unless otherwise specified below.

(2) All RNs 1 to 5 are treated as existing.

Instruction L/ Sister 20 (7) Medium (1') OF, V
RN1-3, YARN%INRN are the ones sent out from the vector instruction buffer 16 and output as they are by the instruction execution determination circuit 18. ALN and TRN are both newly added to the instruction execution determination circuit 1B, and are arithmetic unit designation section and data This is a transfer circuit designation section.

The vector processing device described here focuses on one vector instruction, vector) A/element number.

The data is divided and processed by four vector processing units as follows.

That is, let the vector element number be i.

Vector element number Vector arithmetic processing unit r =
0, 4, 8...41 = 1
, 5 , 9... 5i = 2
, 6.10...6i==3.7.
il...song 7.

The portions of the instruction register 20 other than VARN and INRN are sent to the instruction execution control section 15K in each vector processing unit 4-7. When each of the instruction execution control units 15 receives the unit activation signal 26 from the activation control circuit 21,
Based on the information received from the instruction register 20, the 70 vector processing unit is caused to perform vector processing operations.

Each instruction execution control unit 154! If the vector instruction to be executed is a vector instruction that uses the vector register 9 and the data transfer circuit, such as the LVR instruction or S'rVR instruction, one of VRN1 to VRN5 (LVR instruction or 5T
VR instructions use only one vector register,
Here, it is designated by V'RN1) and TRN are sent to the connection bus selection circuit 24 or 25. At this time.

The connection bus selection circuit 24 or 25 selects the connection bus between the vector register 9 specified by %VRNIK and the data transfer circuit specified by TRN, and activates it. Then, each instruction execution control unit 15 reads the contents from one of the plurality of vector address registers 27 and one of the plurality of increment registers 28 based on YARN and INRN in the instruction register 20. Read out.

The data transfer circuit specified by TRN (hereinafter referred to as the data transfer circuit 11) transfers the contents successively received from the vector address register 27 to the selector 29. It is sent to the storage control unit 2 as an access address via the register 30.

On the other hand, during that time, the contents successively received from the increment register 28 are input to the adder circuit 55 via the quadruple circuit 51 and the register 52, and the sum with the contents of the register 50 is calculated.

This result is then set in the register 30 via the selector 29.

This new content is sent to the storage control unit 2 as an access address in the same way as before.

Thereafter, the same operation is repeated.

Further, the data transfer circuit 11 in the vector arithmetic processing unit 5 calculates the sum of the contents successively received from the vector address register 27 and the contents successively received from the increment register 28 in the adder circuit 54, and adds the sum to the selector 29. It is sent to the storage control unit 2 as an access address via the register 50.

On the other hand, during that time, the contents successively received from the increment register 28 are input to the adder circuit 33 via the quadruple circuit 51 and the register 52, and the sum with the contents of the register 30 is calculated.

This result is then set in the register 50 via the selector 29. This new content is sent to the storage control unit 2 as an access address in the same manner as before. Thereafter, the same operation is repeated.

In addition, in the case of the data transfer circuit 11 in the vector arithmetic processing unit 6, an adder circuit 55 corresponding to the adder circuit 54
The only difference from the above is that the input is the content read from the increment register 28 via the doubling circuit 56.

In addition, in the case of the data transfer circuit 11 in the vector arithmetic processing unit 7, the addition circuit 37 corresponding to the addition circuit 34
The only difference from the above is that the 0 input is the content read from the increment register 2B via the 5x circuit 38.

Note that the address calculation circuit 26 consists of adder circuits 54, 55, 57.2x circuit 56.3x circuit 58.4@circuit 31.
Wow, the figure only shows one prepared for the data transfer circuit 11, but this is not the same as the other data transfer circuits 12 and 1.
5' is also provided.

Therefore, the data transfer circuit specified by TRN is 12 or 1.
In the case of 3, the instruction execution control unit 15 sends a signal to the corresponding address calculation circuit to operate it.

The access address sent from the data transfer circuit 11 in each vector processing unit 4 to 7 to the storage control unit 2 is given to the main storage device 1. If the data transfer circuit specified by TRN is 11 or 12 for fetch, the read data from the main memory 1 is sent to the data transfer circuit 11 or 12 via the signal line 39, and then the connection path selection circuit 24 into the vector register 9 designated by V RN 1. Also,
The data transfer circuit specified by TR,N is 16 for storage.
If so, the read data from the vector register 9 specified by RN1 is sent to the data transfer circuit 13 via the connection path selection circuit 25, and then sent to the main memory device via the signal line 40 and the storage control unit 2. Written to 1.

Each instruction execution control unit 15 &amp;
~3 and ALN are connected to the bus selection circuit 24.25K. At this time, the connection path selection circuits 24 and 25 are set to %VRN.
A connection path between three vector registers 9 indicated by 1 to 5 and one vector arithmetic unit 10 indicated by ALN is selected and activated. After this, data is read from the two selected vector registers 9.

The selected vector arithmetic unit 10 performs the calculation, and the result is written into the selected one vector register 9.

As described above, one vector instruction is divided and processed by the four vector processing units 4-7.

That is, vector operation processing units 4 to 7 each process i MOD4=O, 1M0D, a=1 of L elements.
, iM(JDa=2.1M0Da=s).

Each of the connection path selection circuits 24 and 25 can activate a plurality of connection paths at the same time. As a result, the instruction execution control unit 15 starts executing vector instructions given from the instruction register 20 one after another, if the specified vector register 9, vector arithmetic unit 10, or data transfer circuits 11 to 15 are vacant. Be able to execute multiple vector instructions simultaneously.

Next, control of the number of vector elements processed by each vector processing unit 4 to 7 will be explained using FIG. 3.

Tanipet A/In the instruction execution control section 15 in the arithmetic processing units 4 to 7, one counter is prepared corresponding to each of the vector register, vector arithmetic unit, and data transfer circuit therein. Ru.

%vR when the execution vector instruction is an LV or 8TVR instruction that uses a vector register and data transfer circuit.
A counter corresponding to the vector register and data transfer circuit specified by N1 and TRN.

And if the vector instruction to be executed is a VEA instruction that conveniently uses a vector register and a vector arithmetic unit,
The operation of the counter corresponding to the vector register calculator designated by 3 and ALN is as follows.

In FIG. 3, one of the counters mentioned above is shown as 41, but the same applies to the other counters.

The scalar arithmetic processing unit 3 is also provided.

The data representing the number of vector elements set in the vector length register 17, except for the lower two bits, is set as is in the counter 41 via the correction circuit 42. If the lower two bits of the vector length register 17 are '00', no output is generated from the correction circuit 42. If '0
If 1', vector arithmetic processing unit 40 counter 4
An output is issued from the OR gate 43 in the correction circuit 42 to 1.

Also, if I01', vector arithmetic processing units 4 and 5
An output is issued from the OR gate 46 in the correction circuit 42 and the output line 44 to the counter 41 of the .

Also, if it is '11', the vector arithmetic processing unit)4,5
．． OR gate 4 in correction circuit 42 to counter 41 of 6
Outputs are generated from the output line 6, the output line 44, and the AND gate 45. The counter 41 in each vector arithmetic processing unit 4 to 7 is configured to increment its value by +1 when an output is issued from the correction circuit 42.

When a vector instruction is executed in each of the vector arithmetic processing units 4 to 7, the value of the counter 41 set as described above is decremented by 1 every time one instruction is processed by the vector unit. When the signal is set to 0, an output is output to the signal line 46.

The output of each signal line 46 is sent to a counter 48VC via a priority circuit 47 in the vector calculation control unit 8. Priority circuit 47, counter 4B, and final value register 4
Reference numeral 9 is provided commonly to the vector arithmetic processing units 4 to 7, and the vector register 9. One circuit is prepared corresponding to each of the vector arithmetic unit IQ and data transfer circuits 11 to 15.

Note that the final value register 49 is set to 4 when the activation signal 22 is output. When outputs do not appear on the plurality of signal lines 47 at the same time, the priority circuit 47 applies the respective outputs as they are to the counter 48.

When the outputs appear at the same time, they are shifted by one clock time and fed to the counter 48. The counter 48 counts the output from the priority circuit 47, and when the count value becomes equal to the value of the final value register 49, the comparison circuit 5o outputs an output.The display circuit 19 outputs an output based on the output from the comparison circuit 5o. , its corresponding vector register.

Vector arithmetic unit, data transfer circuit indicator.

Reset to display vacancies.

Vector length register 171' (The number of vector elements to be set may be less than 4%. Therefore, the activation control circuit 21 for activating the necessary number of vector arithmetic processing units is connected to the vector performance control unit 8. During(
C will be prepared.

This will be explained below using FIG. 5.

When the number of vector elements is 4 or more, when the start signal 22 is output from the instruction execution determination circuit 18, the start control circuit 21 sends a unit start signal to all vector) A/arithmetic processing units 4 to 7. 25 is output. Also, as described above, the τ final value register 49 is set to 4 (C). If L is 1, an output is issued from the 1 detection circuit 51 in the startup control circuit 21. Therefore, the unit activation signal 25 to the OR gates 52, 53, and the AND gates 54, 55, and 56 (and thus the vector arithmetic processing unit) 516t7 is blocked.When L is 2, the output from the 2 detection circuit 57 is blocked. Let it be released, Or Gate 52,5
5, the activation signal 23 to the vector arithmetic processing unit 6.7 is blocked by the action of the AND gates 55.56. When L is 3, an output is generated from the 3 detection circuit 58, so the OR gate 55. By the action of the AND gate 56, the two-nit activation signal 23 to the vector arithmetic processing unit 7 is blocked.

Note that when L is less than 4, the number of vector arithmetic processing units to be activated is set in the final tV register 9. In this case, the data to be set in the final value register 49 can be obtained by counting, for example, the unit activation signal 25 sent to each vector processing unit via the same circuit as the priority circuit 47.

The above is an example of dividing one vector instruction into four vector processing units.
The configuration may be such that it can be arbitrarily switched to perform processing using four vector processing units.

For example, in the case of a vector instruction that calculates an inner product or summation, or a vector instruction that performs a first-order cyclic operation.

For example, in order to be able to arbitrarily switch the processing to be performed by one to four vector arithmetic processing units as described above, it is necessary to perform processing using one vector arithmetic processing unit. do it.

In FIG. 5, output iK gates are provided for each of the AND gates 54 to 56 in the activation control circuit 21. When only the vector arithmetic processing unit 4 is allowed to process, the outputs of the AND gates 54 to 56 are prohibited, and when only the vector arithmetic processing units 4 and 5 are made to process, the outputs of the AND gates 55 and 56 are prohibited.

Also, regarding the correction circuit 421τ, all bits of the vector y length register 17 are processed by the vector operation IE! A route where only unit 4 is given as 1, a route where the portion excluding the lower 1 bit is given to vector processing units 4 and 5, and when the lower 1 bit is 11', the counter 41tC+1 of vector processing unit 4 is executed. The system is configured so that these routes can be selected.

If the former route is selected, all vector elements are processed by the vector arithmetic processing unit 4, and in the latter case, the vector elements are dividedly processed by the vector arithmetic processing units 4 and 5.

In addition, when processing is performed only by the vector arithmetic processing unit 4, as shown in FIG. In addition, the vector calculation processing unit 4.
5, the register 52 in the data transfer circuit among them has an increment register 2.
The address calculation circuit 26 is configured so that a value obtained by doubling the value read from B is initially set.

In the former case, it goes without saying that the value set in the final value register 49 must be set equal to the number of vector operation units to be activated.

〔Effect of the invention〕

According to the present invention, since one vector instruction is divided and processed by a plurality of vector arithmetic processing units, the usage efficiency of the vector arithmetic unit and the data transfer circuit can be increased, so that processing speed can be increased.

[Brief explanation of drawings]

Figure 1 shows the overall configuration of an embodiment of the vector processing device of the present invention, and Figure 2 shows details of the vector operation control unit and the data transfer circuit in the vector operation processing unit in Figure 1. Block Diagram FIG. 5 is a block diagram showing details of the vector operation control unit and the instruction execution section in the vector operation processing unit shown in FIG. 1. In the figure, 1... Main storage device, 2... Storage control unit, 5... Scalar arithmetic processing unit. 4-7...--Vector arithmetic processing unit. 8...Vector calculation control unit. 9... Hector register, 10... Vector arithmetic unit. 11-13...Data transfer circuit, 15...
...Instruction execution control unit, 17...Vector length register, 18...
・Instruction execution determination circuit, 21... Start-up control circuit. 26...Address calculation circuit. 41.48... Counter, 42... Correction circuit. 49...Final value register. 50... Comparison circuit. Notebook 1 Diagram I 9 #Science Seven High School Meidai

Claims (4)

[Claims] (1) A plurality of vector registers, a plurality of vector arithmetic units that perform arithmetic processing on vector data received from the vector registers and send the results to the vector registers, and data transfer between the main storage device and the vector registers. A vector processing device having a plurality of data transfer circuits that control a plurality of vector operation processing units including a plurality of vector registers, at least one vector arithmetic unit, and at least one data transfer circuit;
A first storage means in which the total number of vector elements to be processed is set, and a second storage means provided corresponding to each of the vector arithmetic processing units to be processed by each vector arithmetic processing unit. The vector element number converting means sets the number of exponent vector elements, and the vector element number conversion means determines the contents to be set in the second storage means based on the contents set in the first storage means. vector processing device. (2) In the vector processing device according to claim 1, the second storage means includes means for updating the contents by one each time one vector element is processed by the corresponding vector arithmetic processing unit. and a plurality of said second
1. A vector processing device comprising means for detecting that the contents of the storage means have reached a predetermined value. (3) In the vector processing device according to claim 1, the second storage means is provided corresponding to a vector arithmetic unit provided in a corresponding vector arithmetic processing unit. Characteristic vector processing device. (4) In the vector processing device according to claim 1, the second storage means is provided corresponding to a data transfer circuit provided in a corresponding vector arithmetic processing unit. Characteristic vector processing device.