JPS6191940A - Wire bonding structure - Google Patents
Wire bonding structureInfo
- Publication number
- JPS6191940A JPS6191940A JP59213686A JP21368684A JPS6191940A JP S6191940 A JPS6191940 A JP S6191940A JP 59213686 A JP59213686 A JP 59213686A JP 21368684 A JP21368684 A JP 21368684A JP S6191940 A JPS6191940 A JP S6191940A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- wire
- substrate
- bonding
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、基板上にｍｓを略０゜６μｍ以下の厚みで形
成する場合に好適したワイヤボンディング溝造に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wire bonding groove structure suitable for forming ms on a substrate with a thickness of about 0.6 μm or less.
従来の技術
例えば、固体表面を伝搬する音響波を利用してフィルタ
や共振子等の機能を果すよう溝成された弾性表面波（５
ｕｒｆａｃｅ ａｃｏｕｓｔｉｃ ｗａｖｅ 、 Ｓ
ＡＷ）素子においては、当該素子の共振周波数の関係か
ら、圧電性基板上に形成した電極の厚みを略０．５μｍ
以下に設定している。Conventional technology For example, a surface acoustic wave (5.5 cm
surface acoustic wave, S
AW) element, the thickness of the electrode formed on the piezoelectric substrate is approximately 0.5 μm due to the resonance frequency of the element.
It is set below.
ところで、電極の厚みを略０．６μｍ以下とした場合、
電極のボンディング部にワイヤがうまく接合しないとい
う不都合がある。これは、ｌ’ｆｆ、極の膜厚が薄いた
め、ボンディング時の超音波振動が良好に作用しないこ
とが原因と考えられている。By the way, when the thickness of the electrode is approximately 0.6 μm or less,
There is a disadvantage that the wire does not bond well to the bonding part of the electrode. This is thought to be because the ultrasonic vibration during bonding does not work well because the film thickness of l'ff and pole is thin.
このような点から、従来は第４図に示すようにポンディ
ングパッド部Ａを電極１１の厚みより厚くして超音波振
動が電極に良好に作用する状態にしてワイヤボンディン
グを行なっていた。From this point of view, wire bonding has conventionally been carried out by making the bonding pad part A thicker than the electrode 11, as shown in FIG. 4, so that ultrasonic vibrations can effectively act on the electrode.
しかしながら、上記のようにポンディングパッド部のみ
′ＷＬａｉＳの膜厚を厚くするには、製造段階で電極物
質を２回蒸着せねばならないため、作業工程数が多くな
９て非常に面倒であるといった問題がある。However, as mentioned above, in order to increase the thickness of WLaiS only at the bonding pad part, the electrode material must be deposited twice during the manufacturing process, which requires a large number of work steps9 and is very troublesome. There's a problem.
問題点を解決するための手段
本発明者は、水晶、ニオブ酸リチウム、タンクル酸リチ
ウム等の圧電性基板にはアルミ線のワイヤがボンディン
グ可能であるという知見をした。Means for Solving the Problems The present inventor has discovered that aluminum wire can be bonded to a piezoelectric substrate made of quartz, lithium niobate, lithium tankate, or the like.
従って、本発明はこの知見を利用して、電極の厚みを厚
くすることなく、電極上に接続用ワイヤをボンディング
することのできる有効な構造を提供するものである。Therefore, the present invention utilizes this knowledge to provide an effective structure in which a connecting wire can be bonded onto an electrode without increasing the thickness of the electrode.
而して、本発明に係るワイヤボンディング構体は、基板
上に電極を略０，５μｍ以下の厚みで形成するものにお
いて上記ｆｆ１ｔｉのボンディング部に基板が露出した
電極未着部を形成し、接続ワイヤをこの未着部の基板上
面にもボンディングするよう。In the wire bonding structure according to the present invention, in which an electrode is formed on a substrate with a thickness of about 0.5 μm or less, a non-electrode portion where the substrate is exposed is formed in the bonding portion of the ff1ti, and a connecting wire is formed. Also bond to the top surface of this unattached part of the board.
にしたことを特徴としている。It is characterized by the fact that
実施例
第２図は本発明が適用される素子の一例として弾性表面
波素子（共振子）を示し、１はステム、２はステム１上
に取看された圧電性基板、８ａ。Embodiment FIG. 2 shows a surface acoustic wave element (resonator) as an example of an element to which the present invention is applied, in which 1 is a stem, and 2 is a piezoelectric substrate 8a placed on the stem 1.
８ｂ、８ｃ、ａｄは圧電性基板２上に蒸着等によって形
成された電極である。このうち、８ａ。8b, 8c, and ad are electrodes formed on the piezoelectric substrate 2 by vapor deposition or the like. Of these, 8a.
８ｂは交差電極、３ｃ、８ｄは回折格子（反射器）であ
る。これら各電極８ａ〜８ｄは共振周波数の制約上、・
、略０６５μｍ以下の膜厚で形成されていることは既述
の通りである。また電極８ａ〜８ｄの材質はボンディン
グされるワイヤ線との接合の容易性等からアルミニウム
が用いられている。４゜４はステム１に挿設された取出
電極、５，６はこの取出電極４，４と上記電極のボンデ
ィング部Ａとを接続するための導出用リードワイヤで、
例えばアルミニウム（’ＡＮ）線が用いである。8b is a crossed electrode, and 3c and 8d are diffraction gratings (reflectors). Each of these electrodes 8a to 8d is
As described above, the film is formed with a thickness of about 065 μm or less. Furthermore, aluminum is used as the material for the electrodes 8a to 8d due to its ease of joining with the wire wires to be bonded. 4° 4 is an extraction electrode inserted into the stem 1; 5 and 6 are lead wires for connecting the extraction electrodes 4 and 4 with the bonding part A of the electrode;
For example, aluminum ('AN) wire is used.
而して、この構成において、本発明は第１図に示すよう
にボンディング部Ａに基板２が露出した電極未着部６を
形成しく図（５）参照）、ワイヤ５をこの未着部６の基
板上面にもボンディングするようにしたのである（図俤
）参照）。In this configuration, as shown in FIG. 1, the present invention forms a non-electrode part 6 in which the substrate 2 is exposed in the bonding part A (see FIG. 5), and connects the wire 5 to this non-bonded part 6. (See figure 2).
このように未着部６の基板上面にもワイヤをボンディン
グすれば、ワイヤ６は基板２と接着するので、電極を従
来のように厚くしなくても十分な接合強度が得られ、し
かもワイヤは自ずと未着部周囲の電極と接触することと
なるので、ワイヤとして必要な電極と取出電極４，４と
の電気的な接続も良好に行なえる。If the wire is bonded to the upper surface of the substrate in the unattached portion 6 in this way, the wire 6 will be bonded to the substrate 2, so sufficient bonding strength can be obtained without making the electrode thick as in the past. Since it will naturally come into contact with the electrodes around the unattached portion, electrical connection between the electrodes necessary as wires and the extraction electrodes 4, 4 can be made well.
電極未着部６は、マスクパターン設計段階で考慮して壌
けばエツチングするどき同時に除去できるし、また未着
部予定位置を電極形成前にマスクして＄いて電極形成後
にマスクを除くリフトオフ法等によっても形成できる。If the unattached portion 6 of the electrode is taken into account at the mask pattern design stage, it can be removed at the same time as etching.Also, the planned unattached portion can be removed by masking before forming the electrode and then removing the mask after forming the electrode using a lift-off method. It can also be formed by
電極未着部６−の大きさは、ワイヤ５の接着面積より大
きいとワイヤが電極と電気的に接触し得なくな・るので
、ワイヤ５の接着面積より小さいことが必要である。し
かし、あまり小さいと、ワイヤと゛の十分な接着強度が
得られないので、適度な大きさが必要である。従って、
好ましくはワイヤの接着面積に対して４０％〜８０％の
範囲で選定するのがよい。また、電極未着部６の形状は
第１図に示すような方形に限らず、第８図に示すような
円形でもよくその他適宜の形状でもかまわない。
・尚、この実施例では、基板として圧電性基
板を用いているが、本発明はこれに限られるものではな
く、ワイヤ線と接合可能な材料からできた基板であれば
適用できる。同様な意味でワイヤもＡｌ線に限られるも
のではない。The size of the non-electrode portion 6- needs to be smaller than the bonding area of the wire 5, since if the size is larger than the bonding area of the wire 5, the wire will not be able to make electrical contact with the electrode. However, if it is too small, sufficient adhesion strength between the wire and the wire cannot be obtained, so an appropriate size is required. Therefore,
Preferably, it is selected within a range of 40% to 80% of the bonding area of the wire. Further, the shape of the non-electrode portion 6 is not limited to the rectangular shape shown in FIG. 1, but may be circular as shown in FIG. 8 or any other suitable shape.
-Although a piezoelectric substrate is used as the substrate in this embodiment, the present invention is not limited to this, and can be applied to any substrate made of a material that can be bonded to wires. In the same sense, the wire is not limited to Al wire.
発明の詳細
な説明したように本発明に係るワイヤボン、ディング構
体によれば、基板上に電極を略０．６μｍ以下の厚みで
形成する素子において、ポンディ“ング部の膜厚を厚（
す、るどいった面倒な作業を行なわなくても、また電極
をマスキングするといった煩瑣な作業を行なわなぐても
、単に電極未着部を形成するだけでワ′イヤを十分な接
合強度で接合できるといった優れた効果がある。As described in detail, according to the wire bonding structure according to the present invention, in an element in which an electrode is formed on a substrate with a thickness of approximately 0.6 μm or less, the film thickness of the bonding portion is
Wires can be bonded with sufficient bonding strength by simply forming the area where the electrodes are not attached, without having to go through the troublesome work of cleaning or masking the electrodes. There are excellent effects that can be achieved.
第１図囚＠）は本発明のワイヤボンデ・イング構造を説
明する図、第２図は本発明が適用される素子の一例を示
す図、第８図は本発明の他の一実施例を示す図、第４図
は従来のワイヤボンディング構造を説明するための図で
ある。
２・・・基板、８Ｉｌ〜８ｄ・・・電極、６・・・ワイ
ヤ、６・・・電極未着部。
第１図
（Ａ） （ｓ）３ａ（３ｂ）
第２図
第３図
第４図Fig. 1 is a diagram explaining the wire bonding structure of the present invention, Fig. 2 is a diagram showing an example of a device to which the present invention is applied, and Fig. 8 is a diagram showing another embodiment of the present invention. 4 are diagrams for explaining a conventional wire bonding structure. 2... Substrate, 8Il-8d... Electrode, 6... Wire, 6... Electrode not attached part. Figure 1 (A) (s) 3a (3b) Figure 2 Figure 3 Figure 4
Claims (1)
、この電極に導出リードワイヤをボンディングするもの
において、前記電極のボンディング対応位置にボンディ
ング面積の８０％以内で基板が露呈する電極未着部を形
成し、前記ワイヤを前記電極と共に電極未着部の基板上
面にもボンディングすることを特徴とするワイヤボンデ
ィング構体。(1) An electrode is formed on a substrate with a thickness of about 0.5 μm or less and a lead wire is bonded to this electrode, and the substrate is exposed within 80% of the bonding area at the bonding position of the electrode. A wire bonding structure characterized in that a non-attached portion is formed, and the wire is bonded together with the electrode to the upper surface of the substrate in the non-electrode bonded portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59213686A JPS6191940A (en) | 1984-10-11 | 1984-10-11 | Wire bonding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59213686A JPS6191940A (en) | 1984-10-11 | 1984-10-11 | Wire bonding structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6191940A true JPS6191940A (en) | 1986-05-10 |
Family
ID=16643300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59213686A Pending JPS6191940A (en) | 1984-10-11 | 1984-10-11 | Wire bonding structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6191940A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07187222A (en) * | 1993-12-28 | 1995-07-25 | Kenji Yoshikawa | Pack film and production thereof |
-
1984
- 1984-10-11 JP JP59213686A patent/JPS6191940A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07187222A (en) * | 1993-12-28 | 1995-07-25 | Kenji Yoshikawa | Pack film and production thereof |
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