JPS6189669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a fine structure and, simultaneously, a steep junction with self- matching by simultaneously forming a single crystal semiconductor and a polycrystalline semiconductor on a semiconductor layer and an insulating layer respectively, and forming one part of the polycrystalline semiconductor as an electrode of the single crystal semiconductor. CONSTITUTION:After a thermal oxidation film pattern and a LPCVD nitride film pattern are formed on a P (111) substrate 11, an N<+> type buried layer 12 is formed and the patterns are removed, a N type epitaxial layer 13 is formed by a reduced pressure epitaxial method, and next an emitter-collector pattern using a thin oxide film and nitride film is again formed to carry out high pressure oxidation. In this time, an oxide film 15 is formed with its surface made substantially flat. The oxide and nitride film pattern 14 forming collector contact is left to remain and selective epitaxial growth is carried out on the said pattern under a low temperature. A single crystal layer of good quality is formed on an opening in the N type epitaxial layer 13, that is, a single crystal and a polycrystalline layer 18 is formed on the insulating film 15 except the said opening. Next, when the polycrystalline layer 18 is etched by fluoronitrate acetic acid solution, the polycrystalline layer 18 connected to a P type epitaxial layer 16 can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device manufacturing method generally applied to ultra-high-speed, highly integrated semiconductor devices.

Conventional configurations and their problems As semiconductor devices become faster and more highly integrated, microfabrication technology and self-alignment technology are becoming increasingly unreliable. moreover,
In bipolar type devices, thinning and controlling the thickness of the layer is important. Various structures have been proposed to realize these, examples of which are shown in FIG. As is clear from the figure, complex multilayer thin films are repeatedly used to create a self-aligned process. First, as shown in FIG.
．． 3' is formed. At this time, the N+ implant 2 is lifted up in a known manner during the epitaxial growth. After this, a thin oxide film 4. Nitride film 5. Doped polycrystalline silicon 6, further nitrided) 7.
Six layers of oxide film 8 are stacked, and a pattern is formed using a normal exposure wave iho. The above five layers are selectively removed using, for example, dry etching technology, and finally, N16
Layer 3' is etched to form a mesa shape.

Next, a two-layer pattern of an oxide film and a thick nitride film is formed on this, selective oxidation is performed, and isolation is performed using the oxide film 9. Then, the nitride film and oxide film are removed (see Fig. 1b).
). Further, after removing the nitride film 7, when a polycrystalline silicon film 10 is formed and heat treated, the impurities of the doped polycrystalline silicon 6 diffuse into the polycrystalline silicon 10, so that etching:ζ is selectively etched. The concentrated portion is removed, and a polycrystalline silicon film 1o connected to the N epi layer 3 remains. However, since the stepped portion is easily etched, the polycrystalline silicon 10 is often removed from the N-epi layer 3 by a portion. Thereafter, by oxidation treatment, the polycrystalline silicon film 1o is oxidized to form an oxide film 11. After this,
A contact window is opened and aluminum wiring 12 is formed to obtain the final structure shown in FIG. 1d.

As is clear from the above process description, the conventional process itself uses a complex multi-layered thin film, which requires extremely high precision in etching selectivity and controllability, as well as thin film thickness control. , disconnection due to etching,
It is easy for contamination to remain in the recesses, and the groove depth can be easily controlled by etching! In addition to the things necessary for taste, the lifting of the embedding during epitaxial growth and the crystal defects caused by ion implantation, 1. It has various problems such as difficulty in forming a sharp bond.

Although various other methods have been proposed, they all have exactly the same problems, and solutions to these problems are necessary for the practical application of these semiconductor devices.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned problems and provides a new method for manufacturing a semiconductor device that can realize a fine structure (in plane and depth direction) and a steep junction in a self-aligned manner.

Structure of the Invention The present invention is a method for manufacturing a semiconductor device, in which a single crystal semiconductor and a polycrystalline semiconductor are simultaneously formed on a semiconductor layer and an insulating layer, respectively, and a part of the polycrystalline semiconductor is formed as an electrode of the single crystal semiconductor.

Implementation tide. explanation : Embodiments of the present invention will be described below with reference to the drawings.

First, a thin thermal oxide film and an LPGVD nitride film pattern are formed on a P(111)3Ωα substrate 11, a +N buried layer 12 is formed, and the pattern is removed.
Epi layer (~10/1) 1s was deposited with 10
Form to a thickness of 0.3 μm at 50°C. Conventionally, it is about 1.5~
It takes 6 to 10 times as long to form an epitaxial layer with a thickness of 3 lt m compared to the low pressure epitaxial method, and therefore the N buried layer 1
2 was noticeable, whereas with this method,
On the contrary, the uplift has decreased to a very low level. That is, it has been demonstrated that the thickness of the N epi layer 13 can be precisely controlled to a very thin thickness of about 0.3 μm.

Then, 1/j il is formed again using a thin oxide film/nitride film.
An emitter and collector pattern with a width of 1×6 μm in length is formed, and high-pressure oxidation is performed at 850°C. At this time, if the opening is etched and removed by the oxide film thickness A in advance, the oxide film 15 will be formed on almost the surface evenly, as shown in Fig. 2a.
Get the configuration. In FIG. 2B, the oxide film/nitride film pattern 14 in the portion that will become the collector contact is left. In addition, as is clear from (2), the thickness of the oxide film 15 is only about 0.3 μm, which is 1.5 μm thicker than the conventional vertical and horizontal insulation isolation.
It is extremely shallow compared to ~2μm, which not only shortens the process, but also greatly reduces diffusion by shortening thermal oxidation time, reduces crystal defects by reducing stress on the oxide film, and facilitates miniaturization. It has the advantages of

Next, low temperature selective epitaxial growth is performed on this. For example, a molecular beam epitaxial growth method can be applied to this. First, 860°C
After 2 minutes of interface cleaning, epitaxial growth is performed at 650°C and about 6 people/s. Ga molecules and ions are removed using an ionization cell (emission current of about 20 mA, acceleration voltage of 1.5 KV). Extrusion, approximately 2X10/'CI, 0.
It was formed to have a thickness of 2 μrn.

Subsequently, the N epi layer 17 is also formed continuously. The N epi layer 17 also has an ionization cell (emission current of about 15 mA).
, accelerating voltage IKV), the sb molecules and ions are
/c4, 0.3 μm thick.

Through the above operations, a high-quality single crystal layer with a defect sonic intensity of 1010 A or less is formed on the opening of the single crystal N epi layer 13, and a polycrystalline layer 18 is formed on the other insulating film 15.
is formed. In addition, the epitaxial growth temperature was further lowered to 6
When 0Q'C is depressed low, amorphous tU starts to form instead of polycrystalline.

After such low-temperature single-crystal non-single-crystal selective epitaxial growth, the polycrystalline layer 18 is grown in a fluoronitric acid acetic acid solution (1% hydrofluoric acid, 60% nitric acid, 50% acetic acid).
), the polycrystalline layer is etched at a rate approximately 35 times that of single crystal, so that only the polycrystalline layer can be selectively etched, and the polycrystalline layer 18 connected to the P epilayer 16 can be formed. After obtaining the shape shown in FIG. 2 in this manner, a resist pattern is formed, and at least the polycrystalline layer 18 corresponding to the base portion is left and the rest is removed. Further, high-pressure oxidation is performed as described above to form the oxide film 19, and further, if necessary, the CVD oxide film 20 is formed (FIG. 2C).
. Thereafter, the oxide films 19 and 20 on a part of the collector are selectively removed, S is implanted by ion implantation to form a N contact region, and an activation heat treatment is performed at 950 DEG C. for 20 seconds. Roughly open the emitter and part of the collector using an anisotropic dry etching method (gas: C3H8, pressure crab 1 o
om'rorr.

The base electrode 20b is formed by applying Ag as the electrode material and then going through the usual steps.

Obtain emitter electrode 20e and collector electrode 20C (second
Figure d).

What is particularly important in this opening process is that even if some pattern deviation occurs in the opening of the emitter, as shown in FIG. The oxide film on the side wall remains. This makes it possible to form emitters with high self-alignment and a fine pattern, resulting in a high yield of devices with good characteristics9.
It shows that it will be shouted at.

The impurity concentration distribution of the sample obtained above was investigated.

SIMS+ using a part of the monitor (approximately 100 μm opening)
- As a result of the analysis using the method, it was revealed that the impurity distribution in the N PN+ NP layer directly under the emitter does not have a large diffusion that can be detected with the resolution of SIMS.

In addition, as a result of microscopic observation from the surface and scanning electron microscopic observation of the cross section, the columnar single crystal part is vertical to the substrate surface and has a width of 1.
It was confirmed that it extended in μm, and it was confirmed that it had very good self-alignment.

In addition, in FIG. 2d, after leaving the polycrystalline silicon layer 18, a very thin wet oxidation layer of about 20Q thickness is formed,
Next, this thin oxide film is removed by anisotropic dry etching, leaving the oxide film 2 on the sidewalls.

Next, a high melting point metal MO was sputtered for 1500 minutes with a bias of 300 V applied, heat treatment was performed for 80°'030 minutes to silicide the high melting point metal, and the remaining oxide film on the sides was removed by selective etching. The upper refractory metal may be removed and the oxide films 19 and 2Q may be formed.

In this structure, in addition to the above-mentioned moat feature, a high melting point metal or its 11F compound is laminated on the base extraction electrode part 3,
In particular, it is excellent in that the resistance of that part is reduced.

Furthermore, another embodiment of the present invention is shown in FIG.

First, in FIG. 2A, a thin oxide film 21 was first formed by wet oxidation without completely forming an oxide film 15 for insulation isolation, and then an LPGVD polycrystalline silicon layer 22 was formed. Furthermore, the resist is made flat and etched back by dry etching as usual to obtain a structure (FIG. 3) in which the surface is flat and insulation is separated.

The characteristics of the transistor with the structure 1a described above are such that due to reductions in parasitic capacitance, junction capacitance, pace resistance, etc., the uninterrupted wave number is 15 GHz, compared to the conventional 6 to 6 GHz.
It was speeding up to z. In the future, it is expected that the speed will be further increased by optimizing the impurity concentration and layer thickness.

Further, although the explanation has been made regarding the P substrate, it goes without saying that the same applies to the N substrate.

Effects of the Invention As is clear from the above explanation, according to the present invention, microfabrication can be realized in a self-aligned manner through relatively simple steps.

[Brief explanation of drawings]

Figures 1 a - d are process cross-sectional views showing the conventional manufacturing method;
FIGS. &-d are sectional views of the process according to the present invention, and FIG. 3 is a sectional view of a device manufactured according to another embodiment of the present invention. 11...Substrate, 13...N epi layer, 1
6...P epi layer, 17...N epi layer. Name of agent: Patent attorney Toshio Nakao (1st person)
figure

Claims (1)

[Claims] A first electrically conductive region is at least aperture exposed between the insulating layers, and a layer containing a second electrically conductive material is formed thereon by low temperature selective epitaxial growth, followed by a layer containing said first or second electrically conductive material. forming a single crystal composite layer containing a different type of conductor on the opening, forming a polycrystalline layer on the insulating layer, and forming a layer containing the second conductor. selectively removing the polycrystalline layer so that the polycrystalline layer is connected.