JPS6184685A - Memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device for moving an image displayed on a display device to another location within the same screen.

The real deal! The memory control device according to No. 1 regards the memory space as a two-dimensional plane, and is a device for transferring a rectangular area of a part of this two-dimensional plane to another area within the same two-dimensional plane. The image on the display device can be moved to a predetermined location by transferring the memory area.

[Conventional technology]

FIG. 1 shows that in an image memory, for example, a VRAM, two
FIG. 4 is a diagram illustrating a case where image data of an area (SK) first stored in a memory space (S) regarded as an original plane is transferred to a desired area (S!) in the same plane. Typically, such transfer is accomplished by direct memory access (DMA) transfers. That is, the procedure of reading the data loX direction address 33 and writing it to the address 38 of data 1', then reading the address 34 of data 2 and writing it to the address 39 of data r is performed in the order F,
1. Transfer 4 words at a time alternately. As is clear from FIG. 1, the addresses corresponding to addresses 33 to 38 are consecutive, but the last 6 of the row and the first 7 of the next row are discontinuous in terms of addresses. Therefore, in the conventional transfer method, data 1 to 6 are sequentially accessed using addresses 33 to 38, and after the transfer is completed, new parameters are set for transfer of the next block 7 to 12. transfer. This transfer is also performed for the next row 13 (t), and finally the number of rows t is transferred.

[Problems to be Solved by the Invention] In the above-mentioned memory transfer method, each -
The central processing unit ii (
After setting the meter for each line by the CPU, transfer of that line is started.

Therefore, the longer the number of lines t, the more frequently the CPU intervenes, resulting in a decrease in processing efficiency and inhibiting high-speed transfer.

[Means for solving problems]

The present invention provides a memory control device that implements a memory transfer method that solves the above problems, and the memory control device includes a base register for writing and data transfer for setting an initial start address, and a base register for writing and outputting an initial start address. An offset register that sets an offset value for the number of transfers in the row buffer, a row buffer that holds the number of transfers in one section, a column counter that holds and updates the number of rows to be transferred, and a column counter that counts down the number of transfers in the row buffer and updates the number of transfers. A row counter that updates when it reaches
It is equipped with an adder for writing and reading that adds the values of the base register and the offset register, and a memory counter for writing and reading that counts the number of transfers and the offset value and sets the memory address. Set the start address, the number of transfers in one section, the offset value, and the number of lines, and when the first continuous transfer of one section is completed by direct memory access transfer, the transfer is performed based on the start address of the next section calculated by the memory counter. Then, the transfer for the next section continues, and
Transferring the i-th consecutive intervals is accomplished by a memory controller characterized by t-.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram of a memory control device as an embodiment of the present invention. In FIG. 2, l is a write base register, 2 is a read base register, 3 is an offset register, 4 is a row/J buffer, 5 is a column counter, 6 and 7 are adders, 8 is a row counter, 9 is a control circuit, IO and 11 are memory counters, 12 is a multiplexer, 13 is an image memory, and 14 is a ten I
It is a rally register.

In the above configuration, the memory transfer method using tm transfer, which transfers the first memory area (St) of the memory space (S) to the desired memory area (S2) as shown in Figure 1, is basically as follows. It is done as follows. That is, the difference (offset) between the threshold addresses of data 6 and 7 is data 12 and 13.
Assuming that the offset is the same for the following lines, the CPU sets ■, address 33 of 1, which is the start address, before transcription, ■, and then sets that the number of transfers in one section is 6. Then, ■, then set the offsets of 6 and 7, and finally, set the number of lines. As a result, the memory control device described below allows the continuous section l to be
When the transfer of Kamo 6 is completed, the next address of 7 is calculated without CPU intervention, and the transfer of 7 to 12 in the next section is started.

When the transfer of this line is completed, the next 13 addresses are calculated, and the subsequent transfers and transcriptions can be performed in the same manner.

The above basic operation will be explained in detail with reference to the drawings.

As mentioned above (in DMA transfer, writing and reading are performed alternately, but to simplify the explanation, we will explain the read operation. Data bus A is connected to the CPU, and first, set the switch swl to the B side, Initialize base register 2, offset register 3, row buffer and column counter by CPU, i.e. base register 2
Address 33 of data l is input to offset register 3, and addresses 33 to 39 of data l to 6 and addresses 39 to 45 are input as offset values to offset register 3.

In this embodiment, the X-direction addresses of the memory space S are assumed to be addresses 31 to 45 for the sake of explanation. Next switch SWi
is set to A (li+11), the contents of the base register 2 are transferred to the memory counter 10, and the data transfer is started. That is, the offset value of the offset register 3 and the value of the base register 2 are added by the adder 7, the result is taken into the memory counter 10 via the base register 2, and the memory counter IO counts the added value of the base register 2. It is output as the memory address of the transfer destination in section 9.

The number of transfers in one section (-line), ie, 6 in this example, is input to the row buffer γ4, and the number of lines t is input to the column counter 5. The row counter 5 counts down the number of transfers by 6t, and when it reaches O, sends an update to the next row to the 9th pulse ut to L of the base register 2.

As a result, the base register 2 is updated to the address of the data 7 of the next row. In this way, the contents of the memory counter tO and the row counter 8 are updated for each transfer, and when the row counter reaches 70-, which indicates O, the base register is updated and the result of 7 is added by the register 7. is input to the memory counter lO as described above, and the row counter 8
The contents of the column counter 5 are also updated. Such transfer continues until the column counter 5 overflows, and when the overflow occurs, the DMA transfer ends.

When the column counter 5 overflows, it sends a transfer end signal to the control circuit 9.
sends the write/read memory control signal (R/W) to the multiplexer 12, lil! It is sent to the i-image memory 13 and temporary memory 14. The multiplexer 12 switches between writing and reading according to R/%V, and the temporary register 14 transfers the image data to the image memory IJ13.

FIG. 3 shows a timing chart of the above-mentioned memory transfer. As mentioned above (in DMA transfer, writing and reading are performed alternately one byte at a time. Initial values are set in the base register, offset register, row counter, and column counter via CPU data bus A. From then on, DMA transfer is started, address 33 is read from the base register (R) and written to the desired address in the image memory (W).
, hereafter Il! I8I next actual relaxation. R is address 3
When it reaches 8, the row is updated from point B of the row counter. ・The mother pulse U is output and it switches to the next row, and at the same time the column counter counts down the row / 4' pulse Ot t" is output. In this way, When the column counter generates an overflow, it outputs over 70-.glucose 02 and the transfer ends.

[Effects of the Invention] As explained above, according to the present invention, the initial toughness value can be set for all rows consecutively without setting and transferring the mother meter of the next row for each row. Since it is possible to transfer the image data by using the image data transfer method, it is possible to speed up the transfer of image data.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the memory area before transfer of the memory space and the memory area of the transfer destination, FIG. 2 is a diagram of a memory control device as an embodiment of the present invention, and FIG. 5 is a timing chart illustrating memory transfer. 1.2... Base register, 3... Offset register, 4... Row buffer, 5... Column counter, 6.
7... Adder, 8... Row counter, 9... Control circuit, 10.11... Memory counter, 12.
...Multiplexer, 13... Image memory, 14...
Temporary register.

Claims (1)

[Claims] 1. In a memory control device that transfers data in one memory area of a memory space to a different memory area, the device has a base register for writing and reading that sets an initial start address, and an offset for the number of transfers in one section. An offset register that sets a value, a row buffer that holds the number of transfers in one section, a column counter that holds and updates the number of lines to be transferred, and a column counter that counts down the number of transfers in the row buffer and updates when the number of transfers is reached. A write and read adder that adds the values of the base register and the offset register, and a write and read memory counter that counts the number of transfers and offset values and sets the memory address. , the start address, the number of transfers in one section, the offset value, and the number of lines are set in advance before transfer, and when the first continuous transfer of one section is completed by direct memory access transfer, the next section calculated by the memory counter is set. A memory control device characterized in that transfer of the next section is subsequently started based on a start address of , and successive sections are sequentially transferred.