JPS6183048U - - Google Patents

Info

Publication number
JPS6183048U
JPS6183048U JP1984167174U JP16717484U JPS6183048U JP S6183048 U JPS6183048 U JP S6183048U JP 1984167174 U JP1984167174 U JP 1984167174U JP 16717484 U JP16717484 U JP 16717484U JP S6183048 U JPS6183048 U JP S6183048U
Authority
JP
Japan
Prior art keywords
lead terminal
island
lead
semiconductor device
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984167174U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984167174U priority Critical patent/JPS6183048U/ja
Publication of JPS6183048U publication Critical patent/JPS6183048U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Description

【図面の簡単な説明】
第１図はこの考案の１実施例を示すトランジス
タの斜視図、第２図はこの考案の他の実施例を示
すトランジスタの斜視図である。 １・１１：トランジスタ、２・１２：アイラン
ド、３・１３：ペレツト、１４：コレクタリード
端子、９・１９：放熱用リード端子。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 半導体ペレツトと、この半導体ペレツトが
    ボンデイングされるアイランドと、このアイラン
    ドに一体的に形成される第１のリード端子と、前
    記半導体ペレツトの他の電極に接続される第２の
    リード端子とを含み、前記半導体ペレツト付きの
    アイランド及び前記第１、第２のリード端子の一
    部がモールドされてなる半導体装置において、 前記アイランドに一体的に形成される前記第１
    のリード端子とは異なる第３のリード端子を設け
    たことを特徴する半導体装置。 (2) 前記アイランドは、前記第１と第２のリー
    ド端子とは逆方向にモールド外に延設されるフイ
    ンと一体的に形成されるものであり、前記第３の
    リード端子は前記フインに一体的に形成され、モ
    ールド外を前記第１、第２のリード端子と同方向
    に延設されるものである実用新案登録請求の範囲
    第１項記載の半導体装置。 (3) 前記第３のリード端子は、前記第１のリー
    ド端子と同様に一部がモールドされ、モールド外
    部に前記第１のリード端子と同方向に延設される
    ものである実用新案登録請求の範囲第１項記載の
    半導体装置。
JP1984167174U 1984-11-02 1984-11-02 Pending JPS6183048U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984167174U JPS6183048U (ja) 1984-11-02 1984-11-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984167174U JPS6183048U (ja) 1984-11-02 1984-11-02

Publications (1)

Publication Number Publication Date
JPS6183048U true JPS6183048U (ja) 1986-06-02

Family

ID=30724977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984167174U Pending JPS6183048U (ja) 1984-11-02 1984-11-02

Country Status (1)

Country Link
JP (1) JPS6183048U (ja)

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