JPS6182578A - Facsimile coding and decoding device - Google Patents

Abstract

PURPOSE:To detect with high speed a block including a alteration point or a block having dislocation of a directly right scanning point by giving an address to a control circuit to release a bus from the general use processing device and a bus being equipped with an address circuit to renew the value and adding an alterating point detecting device to the coder. CONSTITUTION:After an initial address of a line memory 8 is set to an address generating circuit 13, a general-use processing device 7 sets an output of FF17 to ''1.'' OR of the output with a HOLD signal of DMAC6 is obtained, the HOLD signal is given to the device 7, the releasing of the bus is obtained. The device 7 releases a bus and sends a HLDA signal to an AND gate 14. The gate 14 gives an AND of the said signal and the output of FF17 to an OE terminal of the circuit 13, and renews the address of the circuit 13. When a comparing circuit 19 detects a block including alteration points, the action of the circuit 13 is stopped by resetting FF17, and the HOLD signal is stopped. The device 7 reads an address of a memory 8, knows the address of the above-mentioned block, reads the information and codes it.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a facsimile encoding and decoding device, and more specifically, to a facsimile encoding and decoding device. This invention relates to improvements in encoding and decoding devices for so-called high-speed facsimile machines.

[Background of the invention]

In high-speed facsimile, the following two encoding methods are known. That is, one is so-called one-dimensional encoding, in which the pixel information is scanned in the scanning line direction, the number of consecutive black and white pixels is counted, and this value (this value) is assigned an appropriate code word.The other is the one that has already been transmitted. This is so-called two-dimensional encoding in which the shift between the point of change from white to black or from black to white in the scanning line immediately above the line and the point of change of the scanning line currently being encoded is encoded.

On the other hand, the decoding device decodes the number of consecutive black and white pixels, the deviation from the change point of the scanning line immediately above, etc. from the received code word, and restores it to pixel information.

Conventionally, when an encoding device or a decoding device as described above is configured with a general-purpose processing device such as a microcomputer, a configuration as shown in FIG. 1 is used.

That is, the light reflected on the image 1 to be transmitted passes through the lens 2 and is imaged on the sensor 3, where it is charged and converted. This signal is determined to be white or black through the binarization circuit 4 and is sent out one bit at a time. On the other hand, the general-purpose processing unit 7 processes data as one block, such as a Byte or a Word. For this reason, 2
In order to match the output of the digitization circuit 4 with the processing device, the output of the binarization circuit 4 is converted block by block by a serial/parallel conversion circuit 5.

The result is the direct memory access controller 6 (
The data is written into the line memory 8 under the control of the general-purpose processing unit 7 under the control of the DMAC (hereinafter referred to as DMAC).

The general-purpose processing device 7 reads the image information written in the line memory 8 block by block in a predetermined order according to the program stored in the read-only memory (ROM) 9 and while using RAMIO as a work area. , detect blocks that include a change point that changes from white to black or from black to white, and then calculate the length of consecutive white pixels or black pixels by checking the position of the change point within the block, and Assign a codeword to the result and send the codeword to buffer memo January 1. Buffer memory 1
The code word stored in 1 is read out in accordance with the clock sent from the modem 12, modulated by the modem 12, and then sent out to a transmission line such as a telephone line.

In order to facilitate understanding of the explanation that follows, the procedure for transferring data from the serial/parallel conversion circuit 5 to the line memory 8 using the DMAC 6 will be explained.

(1) After the serial/parallel conversion circuit 5 has accumulated one block of data, it uses the DMA to read the data.
A request signal (DRQ signal) is sent to C6.

(if) When the DMAC 6 receives the DRQ signal, it sends a signal (I
(OLD signal) is output.

(iii) When the general-purpose processing unit 7 receives the HoLD signal, it releases the path and at the same time sends a signal to that effect (Hold Acknowledge I-Io1d Acknowledgment).
1 (abbreviated as LDA signal) below.

6V) When the DMAC 6 receives this HLDA signal, it sends out the address of the line memory 8 where pixel information is to be written to the path. At the same time, DACK (DMA Ackn
owleclge) signal to the serial/parallel converter circuit 5, and read out the pixel information' to the line memory 8. Through the above operations, the pixel information is transferred to the line memory 8.

(V) When the transfer is completed, the serial/parallel conversion circuit 5 stops the DRQ signal. As a result, DMAC6
stops the HOLD signal and returns control of the path to the general-purpose processing device 7.

+vll As a result, the general-purpose processing device 7
The DA signal is stopped and normal encoding processing is restarted.

Although the above configuration is very simple and desirable,
There are the following problems. That is, in this configuration, in order to find the length of consecutive white pixels or black pixels, a block including a change point from a white pixel to a black pixel or from a black pixel to a white pixel is examined using software of a general-purpose processing device. For this reason,
This detection requires a long processing time, making it difficult to speed up the encoding device. For example, if the number of pixels in one scanning line is 2176 pixels = 272 bytes, which is the standard value for high-speed facsimile, and if the general-purpose processing unit 7 is a 3MHz MOS 8-pit microcombi clock, then The processing time for detection is approximately 2 msec per scanning line. In contrast, recent high-speed facsimiles are required to encode each scanning line in 5 msec or less. Within this 5 msec, in addition to detecting the block including the above-mentioned change point, the length of consecutive white pixels and black pixels is counted, the corresponding code word is obtained, and the code word is sent to the buffer memory 11. It is necessary to take steps such as Therefore, the processing time for detecting a block including a change point needs to be made shorter.

[Purpose of the invention]

Therefore, an object of the present invention is to realize a means for speeding up the process of detecting a block including a change point or a block having a deviation from the immediately above scanning line when encoding and decoding of a high-speed facsimile is performed by a general-purpose processing device. That's true.

[Summary of the invention]

In order to achieve the above object, the present invention includes a control circuit that releases a path from a general-purpose processing unit, an address circuit that gives an address to a path and updates the value in a predetermined manner, and a change processor and a controller. When it is detected,
The present invention is characterized in that a change point detection device is added to the encoder to provide a function of returning the path that closes the control circuit for release to the general-purpose processing device.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram of an embodiment of a high-speed facsimile encoding device according to the present invention. In this figure, the inside of the dashed-dotted line is the part that differs from the conventional code arrangement explained in FIG. Components with the same numbers as in FIG. 1 have the same configuration and operation as in FIG. 1, so their explanation will be omitted.

Next, a device for detecting a change point including a change point, which is a main part of the present invention, and its operation will be explained.

(1) The general-purpose processing device 7 sends the address generation circuit 13 to the initial address of the line memory 8 (the address where one block whose change point is to be checked is stored)
After setting, a signal is applied to the set terminal of the slip 70 tube 17 to set the output of the flip-flop 17 to °1''.The output is logically summed with the HOLD signal of DMACts by the OR gate 18 and general processing Device [H to j7
Gives an OLD signal and requests release of the path. In other words, one buff can be used for processing change point detection.

(11) The general-purpose processing device 7 outputs a HOLD signal (OR gate 1
When it receives the output of B, it releases the HLDA signal and sends the HLDA signal to the AND gate 14.

+++b The A N D gate 14 performs a logical product with the output of the above-mentioned flip-flop 17 and the LDA signal, and outputs the output of the address generation circuit 13 to the OE (output, output). The clock signal sent from the clock generation circuit 15 is controlled by the AND gate 16, and the clock signal is supplied to the address generation circuit 13 to update the address.

(I By doing this, the update of L/X of the address generation circuit 13 and the sending of addresses to the path are stopped, and the HOL
The D signal is stopped and the path is returned to the general-purpose processing device 7.

M. The general-purpose processing device 7 reads the address of the line memory 8 indicated by the address generation circuit 13 and learns the address of the block including the change point. Thereafter, the information of the block with the change point is read and the encoding process as explained in FIG. 1 is performed.

The above is an embodiment of the encoding device according to the present invention.
It is clear that the following modifications are also included in the present invention.

(1) The functions enclosed by the broken line in Figure 2 are the functions of the DM explained earlier.
Since the function is equivalent to that of AC, DMAC may be used.

(2) If the above DMAC has multiple channels and is capable of transferring multiple types of data, this DMAC may be used in common with the DMAC 6 for transferring data from the serial/parallel conversion circuit 5 to the line memory. . In this case, the logical OR gate 18 is omitted because the DMAC has a function to logically OR the HOLD signals of a plurality of channels.

FIG. 3 is a circuit diagram showing one embodiment of the comparison circuit 19.

That is, the black and white data for multiple pixels (block information bits) read out from the line memory 8 is subjected to exclusive logic with the white or black value (1 bit) stored in the flip-flop 20 by the general-purpose processing device 7. A summation circuit 21 compares the pixels, and an OR gate 22 checks whether there are mismatched pixels in the block, thereby determining whether or not the block contains a change point.

For example, if the last pixel of the previous block is white ('0'), "O" is stored in the pfrog 20, and °1" is added to one of the multiple exclusive ORs 21. , it is detected that there is a point in that block that automatically changes to black.

Incidentally, instead of being given from the general-purpose processing unit R7 as described above, the value stored in the flip-flop 20 is obtained by delaying the data by one block using the delay element 23 as shown in FIG. The white or black value of a pixel at a certain predetermined position may be used.

FIG. 5 is a circuit diagram of one embodiment of the address generation circuit 13.

As is well known, the path is broken down into an address bus 28 (for example, 16 bits) that transmits address information and a data bus 27 (for example, 8 pits) that transmits data.At this time, the address generation circuit 13 performs the following operations.

(1) The initial address of the line memory 8 is set in the counter 24 from the general-purpose processing device 7 through the data bus 27.

(11) The counter 24 updates the address by the clock transmitted through the AND gate 16.

(+++) The latch 25 converts the output of the counter 24 by 7 from the OE multiplied signal transmitted through the AND gate 14.
It is sent to the dress bus 28.

After detecting the block containing the zero success change point and returning control of the bus to the general purpose processor 7, the general purpose processor 7 reads the address of the block including the change point through the latch 26 and the data bus 27.

The above explanation has been given for the case of a one-dimensional encoding encoding device, but it is also applicable to a two-dimensional encoding encoding device that requires detection of a block that includes a change point between the scanning line immediately above and the scanning line being encoded. The present invention can also be applied to a decoding device for a two-dimensional encoded signal that requires detection of changes in the scan line directly above the received scan line.

In addition, in order to detect the point of change from white to black or from black to white, one block is compared with all white or all black using the comparison circuit 19, and mismatched blocks are detected. However, for example, when pixel information encodes the continuous length of a specific button such as black and white, black and white, black and white black dot, etc.
A mismatched block may be detected by comparing it with the specific button.

Furthermore, although a plurality of pixels are treated as one block in the above, if it is desired to omit the serial/parallel conversion circuit 5, the pixels may be stored in the line memory 8 pixel by pixel.

As described above, according to the present invention, a block including a change point is detected at high speed by adding a flea circuit device instead of software, which is useful for speeding up an encoding device or a decoding device. Furthermore, since the necessary equipment can be replaced with a DMAC that has already been commercialized using LSI, it is easy to implement and has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a conventional example of a high-speed facsimile encoding device using a general-purpose processing device, FIG. 2 is a professional diagram of an embodiment of the high-speed facsimile encoding device according to the present invention, and FIG. ．． FIG. 4 is a circuit diagram illustrating a comparison circuit of the present invention, and FIG. 5 is a circuit diagram illustrating an address generation circuit used in the present invention. 1...Original, 2...S/Z, 3...Sensor, 4...
...Binarization circuit, 5...Serial/parallel conversion circuit, 6...DMAC et al. circle = cello; 7...General purpose processing device, 8...Lie/memo 1c 9. ...ROM, 10...RAM, 1
1... Buffer memo IJ, 12... Modem, 13.
...Address generation circuit, 14.16...Logic AND gate, 15...Clock generation circuit, 17...Flip-flop for controlling path switching 2, 18.22...OR gate, 19...Comparison Circuit, 20... Free lag flop for comparison data storage, 21... Exclusive OR gate, 23... 1-pro delay circuit, 24... Counter, 25.26... Latch, 27 ...data bus, 2
8...Address bus.・ゝ・、Patent attorney Katsuo Ogawa. 'fJt Figure foil 2 Figure No. 312 No. 4

Claims (1)

[Scope of Claims] 1. Comprising a general-purpose processing device and a storage means for storing pixel information connected to the general-purpose processing device via a bus, the pixel information of the storage means is read out block by block, and Encoding that detects the presence or absence of a change point from white to black or from black to white in the read block, and encodes or decodes the facsimile signal by the general-purpose processing device based on the presence or absence of the change point. In the decoding device, in order to detect the presence or absence of the change point, the pixel information is read out block by block from the storage means via the control circuit for releasing the bus from the general-purpose processing device and the released bus. a detection means for detecting the presence or absence of a change point; and an address generation circuit that sends an address of pixel information in blocks to be read out to the detection means via the bus, and updates the address when the detection means does not detect a change point. and a facsimile encoding/decoding apparatus, characterized in that the control circuit is closed and the bus is returned to the general-purpose processing device when a change point is detected by the detection means. 2. In the description of item 1, the control circuit is set by a signal applied from the general-purpose processing device via the bus, reset by the output of the detection means, and when set, sends a HOLD signal to the general-purpose processing device. A facsimile encoding/decoding device consisting of a flip-flop circuit. 3. In the description of item 2, the address generation circuit combines the output signal of the flip-flop and the HLDA of the general-purpose processing device.
A first AND gate having two inputs of signals, and a second AND gate having two inputs of a clock signal and the output of the first AND gate.
and a circuit that uses the output of the first AND gate as an output enable signal and updates an address with the output of the second AND gate. 4. In paragraph 1 or 2, the detection means is:
a single flip-flop for storing a value of white or black; and a plurality of exclusive ORs arranged in parallel for obtaining the exclusive OR of the output of the flip-flop and the bits representing the plurality of pixel information in the block unit. A facsimile encoding/decoding device comprising an OR circuit and an OR gate inputting each output of the plurality of exclusive OR circuits.