JPS6182493A - Manufacture of ceramic circuit board - Google Patents

Manufacture of ceramic circuit board

Info

Publication number
JPS6182493A
JPS6182493A JP20480784A JP20480784A JPS6182493A JP S6182493 A JPS6182493 A JP S6182493A JP 20480784 A JP20480784 A JP 20480784A JP 20480784 A JP20480784 A JP 20480784A JP S6182493 A JPS6182493 A JP S6182493A
Authority
JP
Japan
Prior art keywords
conductor
conductor pattern
substrate
solution
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20480784A
Other languages
Japanese (ja)
Inventor
菊池 紀實
浜村 清人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20480784A priority Critical patent/JPS6182493A/en
Publication of JPS6182493A publication Critical patent/JPS6182493A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (発明の技術分野〕 本発明はセラミック配線基板の製造方法に係り、特に焼
成後に所定の溶液を用いて基板を表面処理する工程を含
むセラミック基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method of manufacturing a ceramic wiring board, and more particularly to a method of manufacturing a ceramic board that includes a step of surface treating the board using a predetermined solution after firing.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

アルミナセラミック基板を使用した多層配線基板は、一
般に次のような工程で作製される。すなわち、アルミナ
グリーンシートと称される未焼成のセラミック基板上に
タングステン(W)またはモリブデン(MO)等の高融
点金属を主体とする導体ペーストを用いてスクリーン印
刷し、所望の導体パターンを形成する。次に、基板と同
材質のアルミナ粉体を主成分とする絶縁体ペーストを用
いてスクリーン印刷し、層間絶縁層を形成する。
A multilayer wiring board using an alumina ceramic substrate is generally manufactured through the following steps. That is, a desired conductor pattern is formed on an unfired ceramic substrate called an alumina green sheet using a conductor paste mainly made of a high melting point metal such as tungsten (W) or molybdenum (MO). . Next, screen printing is performed using an insulating paste mainly composed of alumina powder, which is the same material as the substrate, to form an interlayer insulating layer.

これら導体パターンおよび層間絶縁層の形成を交互に行
なって多層化した後、1500〜1600℃1弱還元性
雰囲気中で焼成を行なうことにより、基板と導体パター
ンおよび層間絶縁層を強固に密着させる。そしてICチ
ップその他の部品を実装し、ワイヤボンディングを可能
とするため、導体パターン上にニッケル(N i ) 
、金(Au)等のめっきを施し、多層配線基板が完成す
る。
After the conductive patterns and interlayer insulating layers are formed alternately to form a multilayer structure, baking is performed at 1500 to 1600° C. in a slightly reducing atmosphere to firmly bond the substrate, conductive patterns, and interlayer insulating layers. Then, in order to mount IC chips and other components and enable wire bonding, nickel (N i ) is placed on the conductor pattern.
The multilayer wiring board is completed by plating with gold (Au) or the like.

しかしながら、このような従来のセラミック配線基板の
製造工程では、特に焼成後の状態で基板上の導体パター
ン以外の領域にも焼成中に飛散した導体等が付着してい
ることが多い。このように基板表面の不要な領域に導体
が付着したままの基板上に無電解めっきを行なうと、め
っき膜が導体パターン上のみならず、それ以外の領域に
付着している導体の上にも形成されてしまう。このため
、めっき金属であるNt、Au等の高価な材料が無駄に
消費されることになりコスト面で問題となるばかりでな
く、最悪の場合は不要な領域上に形成されためっきによ
って導体パターン間が短絡されるという問題がある。
However, in such a conventional manufacturing process of a ceramic wiring board, conductors scattered during firing often adhere to areas other than the conductor pattern on the board, especially after firing. If electroless plating is performed on a substrate with conductors still attached to unnecessary areas on the substrate surface, the plating film will not only be deposited on the conductor pattern but also on the conductors attached in other areas. It will be formed. For this reason, expensive materials such as Nt and Au, which are plated metals, are wasted and not only is there a problem in terms of cost, but in the worst case, the plating formed on unnecessary areas may lead to conductive patterns. There is a problem of short circuit between the two.

また、上記のように焼成後の状態で基板上の導体パター
ン以外の領域に付着している導体は付着力がかなり強く
、しかも極めて多数の個所に分散しているので、例えば
顕微鏡等でチェックして機械的に除去しようとすると非
常に手間がかかり、また基板表面や導体パターン等を誤
って傷付けてしまい、かえって歩留りを低下させるおそ
れがあった。
In addition, as mentioned above, the adhesion of the conductor that adheres to areas other than the conductor pattern on the substrate after firing is quite strong and is dispersed in a large number of places, so it should be checked using a microscope, etc. If an attempt is made to remove the material mechanically, it is very time consuming and there is a risk of accidentally damaging the substrate surface, conductor pattern, etc., which may actually reduce the yield.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、焼成後のめつき工程においてめっき膜
が基板上の導体パターン以外の領域に付着するのを防止
できるセラミック配線基板の製造方法を提供することに
ある。
An object of the present invention is to provide a method for manufacturing a ceramic wiring board that can prevent a plating film from adhering to areas other than the conductor pattern on the board during the plating process after firing.

〔発明の概要〕[Summary of the invention]

本発明に係るセラミック基板の製造方法は、セラミック
基板上に導体ペーストを用いて所望の導体パターンを形
成し焼成した後、前記セラミック基板を前記導体ペース
トを侵す溶液中に浸漬することにより、前記セラミック
基板上の前記導体パターン以外の領域に付着している導
体を剥離し、しかる後前記導体パターン、上にめっきを
施す工程を含むことを特徴とする。
The method for manufacturing a ceramic substrate according to the present invention includes forming a desired conductive pattern on a ceramic substrate using a conductive paste and firing it, and then immersing the ceramic substrate in a solution that corrodes the conductive paste. The method is characterized in that it includes a step of peeling off the conductor attached to the area other than the conductor pattern on the substrate, and then plating the conductor pattern.

ここで、導体ペーストがタングステンまたはモリブデン
を主体とするものである場合、前記溶液はフェリシアン
化カリウムと水酸化ナトリウムを含む水溶液が適当であ
る。また、セラミック基板を前記溶液中に浸漬してセラ
ミック基板上の導体パターン以外の領域に付着した導体
を剥離するに際し、前記溶液に超音波撮動を付与して、
いわゆる超音波洗浄を行なうとより効果的である。
Here, when the conductive paste is mainly composed of tungsten or molybdenum, the solution is suitably an aqueous solution containing potassium ferricyanide and sodium hydroxide. Further, when the ceramic substrate is immersed in the solution and the conductor attached to the area other than the conductor pattern on the ceramic substrate is peeled off, the solution is subjected to ultrasonic imaging,
It is more effective to perform so-called ultrasonic cleaning.

(発明の効果) 本発明によれば、導体ペーストにより導体パターンを形
成し焼成した後、めっき工程の前に基板を溶液中に浸漬
し導体パターン以外の領域に付着している導体を剥離す
ることにより、めっき工程時にめっき膜が導体パターン
以外の領域上に形成されてしまうことはない。
(Effects of the Invention) According to the present invention, after forming a conductor pattern using a conductor paste and baking it, the substrate is immersed in a solution before the plating process to peel off the conductor attached to areas other than the conductor pattern. This prevents a plating film from being formed on areas other than the conductor pattern during the plating process.

従って、めっき金属であるNi、Au等の高価な材料を
浪費することがなく、コストの低減を図ることができる
。また、めっきによって導体パターン間が短絡されると
いうような不良も生じない。
Therefore, expensive materials such as Ni and Au, which are plating metals, are not wasted, and costs can be reduced. Further, defects such as short circuit between conductive patterns due to plating do not occur.

また、焼成後における基板表面のチェッ7り工程が不要
ないしは極く簡単で済み、農産性が向上する。
Further, the step of checking the substrate surface after firing is unnecessary or extremely simple, and agricultural productivity is improved.

さらに、導体パターン以外の領域に付着しためつき膜を
機械的に除去する方法と異なり、基板表面や導体パター
ンを傷付けることがなく、それだけ歩留りも向上するこ
とになる。しかも、副次的効果として上記溶液による処
理によって導体パターンの表面が適度に荒れることによ
り、めっき膜の付着力が増し、配線基板の信頼性が向上
するという利点もある。
Furthermore, unlike the method of mechanically removing the taming film adhering to areas other than the conductor pattern, this method does not damage the substrate surface or the conductor pattern, and the yield is improved accordingly. Moreover, as a secondary effect, the surface of the conductive pattern is appropriately roughened by the treatment with the solution, which increases the adhesion of the plating film and improves the reliability of the wiring board.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の詳細な説明する。 The present invention will be explained in detail below.

m上 アルミナ(Aj2203 >を93%含む無機質粉体を
用い、ドクターブレード法によってセラミック基板とし
てのアルミナグリーンシート(未焼成シート)を得た。
An alumina green sheet (unfired sheet) as a ceramic substrate was obtained by a doctor blade method using an inorganic powder containing 93% of alumina (Aj2203).

このアルミナグリーンシート上にタングステンを主体と
する導体ペーストを用いてス2り一印刷を行ない、乾燥
させて所望の導体パターンを形成した。次に、アルミナ
グリーンシートと同材質の無機質粉体を主成分とする絶
縁体ペーストを用いて同様にスクリーン印刷、乾燥して
層間絶縁層を形成した。これら導体パターンおよび層間
絶縁層の印刷・乾燥を交互に複数回繰返し、導体パター
ンが3層の多層配線構造とした。
Printing was performed on this alumina green sheet using a conductor paste mainly composed of tungsten, and the paste was dried to form a desired conductor pattern. Next, an insulating paste containing the same inorganic powder as the alumina green sheet as its main component was similarly screen printed and dried to form an interlayer insulating layer. The printing and drying of these conductor patterns and interlayer insulating layers were alternately repeated several times to obtain a multilayer wiring structure with three layers of conductor patterns.

次に、この多層配線構造の基板を1550℃〜1600
℃9弱還元性雰囲気中で焼成した。このとき得られた焼
成済み基板のうち30%以上の基板に、導体パターン以
外の領域上へのタングステンの付着が認められた。
Next, the board with this multilayer wiring structure was heated to 1550°C to 1600°C.
It was fired in a slightly reducing atmosphere at 9°C. At least 30% of the fired substrates obtained at this time were found to have tungsten attached to areas other than the conductor patterns.

そこで、この不要なタングステンが付着した基板をフェ
リシアン化カリウム (K3 Fe (ON)s )100gと水酸化ナトリ
ウム(NaOH)100G、水1000ccの水溶液中
に浸漬し、超音波洗浄を150秒間行なった。
Therefore, the substrate with this unnecessary tungsten attached was immersed in an aqueous solution of 100 g of potassium ferricyanide (K3 Fe (ON)s), 100 G of sodium hydroxide (NaOH), and 1000 cc of water, and ultrasonic cleaning was performed for 150 seconds.

次いで、基板を1分間水洗した後、エアブロ−で基板表
面を乾燥させた。さらに基板をアセトン中に入れ、10
〜15分間超音波洗浄した。このような処理を行なった
基板は、顕微鏡でチェックしても、所望の導体パターン
以外の個所にはタングステンの付着は認められなかった
。 次に、このようにして導体パターン以外の領域上に
付着していたタングステンが溶液による表面処理で剥離
・除去された基板の導体パターン上に、無電解めっき法
で下地層としてNi2表面層としてAuを付着させた。
Next, the substrate was washed with water for 1 minute, and then the surface of the substrate was dried with air blow. Furthermore, put the substrate in acetone and
Ultrasonic cleaned for ~15 minutes. When the substrate subjected to such treatment was checked under a microscope, no tungsten was found to be attached to any part other than the desired conductor pattern. Next, on the conductor pattern of the substrate from which the tungsten that had adhered to areas other than the conductor pattern was peeled off and removed by surface treatment with a solution, an underlayer of Ni2 and Au as a surface layer was applied by electroless plating. was attached.

このめっき工程の後、顕微鏡で再びチェックしたところ
、所望の導体パターン以外の領域にはめつき膜は全く認
められず、100%の歩留りが得られた。
After this plating step, when it was checked again using a microscope, no plating film was observed in areas other than the desired conductor pattern, and a yield of 100% was obtained.

友1九り 実施例1におけるタングステンに代えてモリブデン(M
O)を主体とする導体ペーストを用い、それ以外の工程
は実施例1と全く同様にして多層配線基板を作製したと
ころ、めっき工程終了後においてやはり不要なめっき膜
の付着は全く認められず、歩留りは100%であった。
In place of tungsten in Example 1, molybdenum (M
When a multilayer wiring board was manufactured using a conductor paste mainly composed of O) and the other steps were exactly the same as in Example 1, no unnecessary plating film was observed after the plating process was completed. The yield was 100%.

なお、本発明は上記実施例に限定されるものではなく、
例えば導体ペーストがW、MOの場合、基板上の導体パ
ターン以外の領域に付着した導体を剥離するための溶液
としては、前述したもののほか過マンガン酸カリウムや
水酸化カリウム等と水酸化ナトリウムの組合せを用いて
も同様の効果が得られることが確認された。
Note that the present invention is not limited to the above embodiments,
For example, when the conductor paste is W or MO, the solution for peeling off the conductor attached to areas other than the conductor pattern on the board may be a combination of potassium permanganate, potassium hydroxide, etc., and sodium hydroxide, in addition to the solutions mentioned above. It was confirmed that the same effect could be obtained by using .

また、実施例ではグリーンシート、すなわち未焼成のセ
ラミック基板上に導体パターンおよび層間絶縁層を形成
した後、基板と導体パターンおよび層間絶縁層をまとめ
て焼成したが、焼成済みのセラミック基板上に導体パタ
ーン等を形成し、その後焼成してもよい。さらに、実施
例では多層配線基板の製造方法について述べたが、本発
明はセラミック基板上に導体ペーストを印刷等により形
成し、焼成の後、導体パターン上にめっきを施す工程を
含むものであれば、単層配線基板の製造にも有効である
In addition, in the example, a conductor pattern and an interlayer insulating layer were formed on a green sheet, that is, an unfired ceramic substrate, and then the substrate, the conductor pattern, and an interlayer insulating layer were fired together. A pattern or the like may be formed and then fired. Furthermore, although the method for manufacturing a multilayer wiring board has been described in the embodiment, the present invention may include a process of forming a conductive paste on a ceramic substrate by printing or the like, and plating the conductive pattern after firing. , is also effective for manufacturing single-layer wiring boards.

Claims (3)

【特許請求の範囲】[Claims] (1)セラミック基板上に導体ペーストを用いて所望の
導体パターンを形成し焼成した後、前記セラミック基板
を前記導体ペーストを侵す溶液中に浸漬することにより
、前記セラミック基板上の前記導体パターン以外の領域
に付着している導体を剥離し、しかる後前記導体パター
ン上にめつきを施す工程を含むことを特徴とするセラミ
ック配線基板の製造方法。
(1) After forming a desired conductor pattern on a ceramic substrate using a conductor paste and firing it, the ceramic substrate is immersed in a solution that corrodes the conductor paste, thereby forming a conductor pattern other than the conductor pattern on the ceramic substrate. A method for manufacturing a ceramic wiring board, comprising the steps of peeling off a conductor adhering to a region, and then plating the conductor pattern.
(2)前記導体ペーストはタングステンまたはモリブデ
ンを主体とするものであり、前記溶液はフェリシアン化
カリウムと水酸化ナトリウムを含む水溶液であることを
特徴とする特許請求の範囲第11記載のセラミック配線
基板の製造方法。
(2) Manufacturing the ceramic wiring board according to claim 11, wherein the conductive paste is mainly made of tungsten or molybdenum, and the solution is an aqueous solution containing potassium ferricyanide and sodium hydroxide. Method.
(3)前記セラミック基板を前記導体ペーストを侵す溶
液中に浸漬することにより、前記セラミック基板上の前
記導体パターン以外の領域に付着している導体を剥離す
るに際し、前記溶液に超音波振動を付与することを特徴
とする特許請求の範囲第1項記載のセラミック配線基板
の製造方法。
(3) By immersing the ceramic substrate in a solution that corrodes the conductor paste, ultrasonic vibration is applied to the solution when peeling off the conductor attached to areas other than the conductor pattern on the ceramic substrate. A method of manufacturing a ceramic wiring board according to claim 1, characterized in that:
JP20480784A 1984-09-29 1984-09-29 Manufacture of ceramic circuit board Pending JPS6182493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20480784A JPS6182493A (en) 1984-09-29 1984-09-29 Manufacture of ceramic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20480784A JPS6182493A (en) 1984-09-29 1984-09-29 Manufacture of ceramic circuit board

Publications (1)

Publication Number Publication Date
JPS6182493A true JPS6182493A (en) 1986-04-26

Family

ID=16496687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20480784A Pending JPS6182493A (en) 1984-09-29 1984-09-29 Manufacture of ceramic circuit board

Country Status (1)

Country Link
JP (1) JPS6182493A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0480038A1 (en) * 1990-04-16 1992-04-15 Denki Kagaku Kogyo Kabushiki Kaisha Ceramic circuit board
JP2594475B2 (en) * 1990-04-16 1997-03-26 電気化学工業株式会社 Ceramic circuit board
JPH09181423A (en) * 1990-04-16 1997-07-11 Denki Kagaku Kogyo Kk Ceramic circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0480038A1 (en) * 1990-04-16 1992-04-15 Denki Kagaku Kogyo Kabushiki Kaisha Ceramic circuit board
US5354415A (en) * 1990-04-16 1994-10-11 Denki Kagaku Kogyo Kabushiki Kaisha Method for forming a ceramic circuit board
JP2594475B2 (en) * 1990-04-16 1997-03-26 電気化学工業株式会社 Ceramic circuit board
EP0480038B1 (en) * 1990-04-16 1997-07-09 Denki Kagaku Kogyo Kabushiki Kaisha Ceramic circuit board
JPH09181423A (en) * 1990-04-16 1997-07-11 Denki Kagaku Kogyo Kk Ceramic circuit board

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