JPH03270193A - Method of manufacturing printed board - Google Patents
Method of manufacturing printed boardInfo
- Publication number
- JPH03270193A JPH03270193A JP6815390A JP6815390A JPH03270193A JP H03270193 A JPH03270193 A JP H03270193A JP 6815390 A JP6815390 A JP 6815390A JP 6815390 A JP6815390 A JP 6815390A JP H03270193 A JPH03270193 A JP H03270193A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating
- electroless
- solder plating
- surface layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000007747 plating Methods 0.000 claims abstract description 56
- 229910000679 solder Inorganic materials 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000002344 surface layer Substances 0.000 claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 239000010949 copper Substances 0.000 abstract description 7
- 230000008018 melting Effects 0.000 abstract description 6
- 238000002844 melting Methods 0.000 abstract description 6
- 238000004070 electrodeposition Methods 0.000 abstract description 2
- 238000005868 electrolysis reaction Methods 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 9
- 238000011282 treatment Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要］
プリント基板の製造方法に関し、
半田めっきの再溶融性および実装性を改善するため、
回路形成のため表面層部にエツチング処理が施された半
田めっきプリント基板に対して無電解半田めっき処理を
行うことにより構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a printed circuit board, in order to improve remelting properties and mounting properties of solder plating, a solder plated printed circuit board whose surface layer is etched for circuit formation is provided. It is constructed by performing electroless solder plating treatment on the surface.
（産業上の利用分野） 本発明は、プリント基板の製造方法に関する。(Industrial application field) The present invention relates to a method for manufacturing a printed circuit board.
さらに詳しくは、本発明は、エツチング処理が完了した
半田めっきプリント基板において、電解半田めっきを再
溶融（ヒューズイング）するに際して、その前処理とし
て無電解半田めっきを施すプリント基板の製造方法に関
する。More specifically, the present invention relates to a printed circuit board manufacturing method in which electroless solder plating is performed as a pretreatment for remelting (fusing) the electrolytic solder plating on a solder plated printed circuit board that has undergone etching processing.
プリント基板においては、近年、高密度化、多層化、細
線パターン化をますます進展し、ＳＭＴと呼ばれる表面
実装型基板が主として用いられるようになっている。こ
のため、ＳＭＴ基板の実装品質を左右する表面パターン
部やパッド部の半田めっき品質が重要視されている。In recent years, printed circuit boards have become increasingly dense, multilayered, and patterned with fine lines, and surface-mounted circuit boards called SMT have come to be mainly used. For this reason, the quality of solder plating on the surface pattern portion and pad portion, which affects the mounting quality of the SMT board, is considered important.
〔従来の技術］ 従来のプリント基板の製造プロセスを第４図に示す。[Conventional technology] FIG. 4 shows a conventional printed circuit board manufacturing process.
電解半田めっき（ｔｌ）を施した基板に対し、回路形成
のため表面層エツチング（ｔ２）を行う。次いで、表面
の半田めっきを再溶融（ｔ４）させ、半田めっき組成を
共晶付近（錫６３％：鉛３７％）とし、かつ、表面組織
を均一かつ緻密にして、実装性を改善する。ここで、表
面層エツチングＤｔ）の処理後、再溶融（（４）処理に
て、パターン側面まで半田めっきで覆うことを目的とし
て無電解錫めっき（ｔ、）を施すことも知られている。Surface layer etching (t2) is performed on the substrate that has been subjected to electrolytic solder plating (tl) to form a circuit. Next, the solder plating on the surface is remelted (t4) to make the solder plating composition near eutectic (63% tin: 37% lead), and to make the surface structure uniform and dense to improve mounting performance. It is also known that after surface layer etching (Dt), electroless tin plating (t,) is performed for the purpose of covering the side surfaces of the pattern with solder plating in remelting ((4)).
この錫めっき処理により、再溶融時にパターン側面にま
で半田めっきの被覆を施して、半田めっきヒゲ（スリバ
）を防ぐことができる。This tin plating treatment allows the side surfaces of the pattern to be coated with solder plating during remelting, thereby preventing solder plating slivers.
即ち、第５図に示すように、表面層エツチング後、銅め
っき（１）上に半田めっき（２）が施されたパターンが
得られる（第５図イ）。かかる基板に対して無電解錫め
っき（３）を施しく第５図口）、次いで再溶融を行うと
パターン側面まで半田めっきで覆われたパターンが得ら
れる（第５図ハ）。That is, as shown in FIG. 5, after etching the surface layer, a pattern is obtained in which solder plating (2) is applied on copper plating (1) (FIG. 5A). When such a substrate is subjected to electroless tin plating (3) (FIG. 5) and then remelted, a pattern is obtained in which the sides of the pattern are covered with solder plating (FIG. 5C).
上記の如く、半田めっきヒゲを防ぐために、再溶融処理
前に、無電解錫めっきが０．１〜０．５μｍ程度の厚さ
で施されるのである。As mentioned above, in order to prevent solder plating whiskers, electroless tin plating is applied to a thickness of about 0.1 to 0.5 μm before remelting treatment.
しかし、無電解錫めっき処理後、半田めっきを再溶融す
る場合に、無電解錫めっき後の放置時間が長い場合や、
再溶融時に基板樹脂部の水分の除去のために長時間の予
備乾燥を要する、板厚の厚い基板を再熔融する場合には
、半田溶融性が不良になるという問題があった。However, when remelting the solder plating after electroless tin plating, there are cases where the left time after electroless tin plating is long,
When remelting a thick board that requires a long period of preliminary drying to remove moisture from the resin portion of the board during remelting, there is a problem in that the solder meltability is poor.
本発明は、表面層部にエツチング処理が施された半田め
っきプリント基板の半田めっきの再溶融性および実装性
を改善することのできる、プリント基板の製造方法を提
供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a printed circuit board that can improve the remelting performance and mounting performance of solder plating of a solder plated printed circuit board whose surface layer portion has been subjected to an etching process.
本発明によれば、上記課題を解決するため、回路形成の
ため表面層部にエツチング処理が施された半田めっきプ
リント基板に対して無電解半田めっき処理を行うことを
特徴とするプリント基板の製造方法が提供される。According to the present invention, in order to solve the above-mentioned problems, a printed circuit board is manufactured in which an electroless solder plating process is performed on a solder plated printed circuit board whose surface layer has been etched for circuit formation. A method is provided.
第１図は、本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.
表面層のエツチング後に銅めっき（１）および電解法で
形成された半田めっき（２）からなるパターンが得られ
る（第１図イ）。かかる基板に対して無電解半田めっき
（４）を施しく第１図口）、次いで再溶融を行うとパタ
ーン側面まで半田めっきで覆われたパターンが得られる
（第１図へ）。After etching the surface layer, a pattern consisting of copper plating (1) and solder plating (2) formed by electrolytic method is obtained (FIG. 1A). When such a substrate is subjected to electroless solder plating (4) (see Figure 1) and then remelted, a pattern is obtained in which the sides of the pattern are covered with solder plating (see Figure 1).
従来技術においては、表面層エツチング後、無電解錫め
っきが施されていた。これに対し、無電解半田めっきは
、錫と鉛との比が６０％：４０％になる電着組成を有し
、その組成が下地となる電解法で形成された半田めっき
の組成（錫：鉛−６＝４）とほとんど等しくなるため、
再溶融時の半田溶融−ゝ−′ 性および実装時の半田溶
融性（即ち実装性）が改善されることとなる。In the prior art, electroless tin plating was applied after surface layer etching. On the other hand, electroless solder plating has an electrodeposition composition in which the ratio of tin to lead is 60%:40%, and this composition is the base composition of the solder plating formed by the electrolytic method (tin: lead-6=4), so
The solder meltability during remelting and the solder meltability during mounting (ie, mounting performance) are improved.
第２図および第３図は、それぞれ、本発明の方法の一実
施例を示すフローチャートである。FIGS. 2 and 3 are flowcharts each illustrating one embodiment of the method of the present invention.
第２図は電解半田めっきを再溶融する場合の例であり、
電解半田めっき厚は表面で約７〜９μ餉に設定される。Figure 2 is an example of remelting electrolytic solder plating.
The electrolytic solder plating thickness is set to about 7 to 9 μm on the surface.
また、第３図は、再溶融を行わない場合の例であり、電
解半田めっき厚は約２０〜４０μ陽に設定される。いず
れの場合も、表面層エツチングで回路形成されたパター
ンやパッドの側面は銅めっきがむき出しとなるが、市販
の薬品を用い、約０．１〜３μｍ程度のめっき厚に無電
解半田めっきを行うことにり、それらの側面までほぼ完
全に半田で覆うことが可能となる。Further, FIG. 3 shows an example in which remelting is not performed, and the electrolytic solder plating thickness is set to approximately 20 to 40 μm. In either case, the copper plating is exposed on the sides of the patterns and pads where circuits are formed by surface layer etching, but electroless solder plating is performed using commercially available chemicals to a plating thickness of approximately 0.1 to 3 μm. In particular, it is possible to almost completely cover those sides with solder.
第２図に示す如き方法により、５ Ｘ ６１０Ｘ ５１
０１の寸法を有する半田めっき基板を次のように処理し
た。即ち、表面層エツチング後、酸性アクチヘータ処理
（ＸＰ−８９５２１０Ｘ）を常温で２分間行い、常温で
１分間づつ２回水洗し、ブリデイツプ処理（ＸＰ−８９
５１−１１０すを６５±３°Ｃで１分、ソルダーポジッ
ト（無電解めっき）処理（ＴＩＮ−ＸＰ−８９５５Ａ
５０χ、ＬＥＡＤ−ＸＰ−８９５５８５０Ｘ）を６５±
３°Ｃで１分、次いでポストデイツプ処理（ＸＰ−８９
５２２χ）を常温で１分行い、常温で１分間づつ２回水
洗し、最後に４５±５°Ｃでブロア乾燥を行った。なお
、前記各処理に用いた処理液は、全てシブレイ社製の市
販薬品であった。By the method shown in Fig. 2, 5 x 610 x 51
A solder plated substrate having dimensions of 0.01 was processed as follows. That is, after etching the surface layer, acidic actiator treatment (XP-895210X) was performed at room temperature for 2 minutes, followed by washing with water twice at room temperature for 1 minute each, followed by bridging treatment (XP-89
51-110 at 65±3°C for 1 minute, solderpolyte (electroless plating) treatment (TIN-XP-8955A
50χ, LEAD-XP-8955850X) to 65±
1 minute at 3°C, then post dip treatment (XP-89
522χ) for 1 minute at room temperature, washed twice with water for 1 minute each at room temperature, and finally dried with a blower at 45±5°C. The treatment liquids used in each of the above treatments were all commercially available chemicals manufactured by Sibley.
次いで再溶融を行ったところ、溶融性は極めて良好であ
り、溶融前の半田組成が５８．０〜６４．５％（平均６
２．８％）であったのに対して、溶融後の半田組戒は５
８．９〜６４．７％（平均６３．２％）とばらつきの小
さいものであった。これに対し、上記無電解半田めっき
の代わりに常法による無電解錫めっきを施した場合には
、溶融前の半田組成が５８．７〜６４．０％（平均６２
．５％）であったのに対して、溶融後の半田＆［ｌ戒は
５７．０〜６６．８％（平均６４，１％）とばらつきの
大きいものであった。Next, when remelting was performed, the meltability was extremely good, and the solder composition before melting was 58.0 to 64.5% (average 64.5%).
2.8%), whereas the solder kumikai after melting was 5%.
The variation was 8.9 to 64.7% (average 63.2%). On the other hand, when electroless tin plating is performed by a conventional method instead of the electroless solder plating described above, the solder composition before melting is 58.7 to 64.0% (average 62%).
．． 5%), whereas the solder after melting had a large variation of 57.0 to 66.8% (64.1% on average).
第４図は、従来の半田めっきプリント基板の製造プロセ
スを示すフローチャートである。FIG. 4 is a flowchart showing a conventional solder-plated printed circuit board manufacturing process.
第５図は、従来の半田めっきプリント基板のパターンを
示す模式図である。FIG. 5 is a schematic diagram showing a pattern of a conventional solder-plated printed circuit board.
１−一一銅めっき、２−電解半田めっき、３−無電解錫
めっき、４−無電解半田めっき。1-11 copper plating, 2-electrolytic solder plating, 3-electroless tin plating, 4-electroless solder plating.
以上に説明したように、本発明によれば、表面層エツチ
ングで回路形成されたパターンや実装用パッドの側面（
銅めっき）に無電解半田めっきが付着する結果、半田め
っきの濡れ性が良好でかつ細線パターンのショート不良
の原因となるめっきヒゲを完全に防止することができ、
プリント基板の実装品質の向上に寄与するところが大き
い。As explained above, according to the present invention, the side surface (
As a result of the electroless solder plating adhering to the copper plating (copper plating), the solder plating has good wettability and can completely prevent plating whiskers that cause short circuit defects in fine line patterns.
This greatly contributes to improving the mounting quality of printed circuit boards.
第１図は、本発明の原理説明図である。
第２図および第３図は、それぞれ、本発明の方法の一実
施例を示すフローチャートである。
イ
口
第３図
５４FIG. 1 is a diagram explaining the principle of the present invention. FIGS. 2 and 3 are flowcharts each illustrating one embodiment of the method of the present invention. Iguchi Figure 3 54
Claims (1)
た半田めっきプリント基板に対して無電解半田めっき処
理を行うことを特徴とするプリント基板の製造方法。1. A method for manufacturing a printed circuit board, characterized in that electroless solder plating is performed on a solder plated printed circuit board whose surface layer has been etched for circuit formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6815390A JPH03270193A (en) | 1990-03-20 | 1990-03-20 | Method of manufacturing printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6815390A JPH03270193A (en) | 1990-03-20 | 1990-03-20 | Method of manufacturing printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03270193A true JPH03270193A (en) | 1991-12-02 |
Family
ID=13365512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6815390A Pending JPH03270193A (en) | 1990-03-20 | 1990-03-20 | Method of manufacturing printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03270193A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06302940A (en) * | 1993-04-12 | 1994-10-28 | Nec Corp | Formation of solder film |
| US7546681B2 (en) | 1999-10-12 | 2009-06-16 | Tessera Interconnect Materials, Inc. | Manufacturing method for wiring circuit substrate |
| US8162152B2 (en) | 2005-10-04 | 2012-04-24 | Jms Co., Ltd. | Blood filter device and method of manufacturing the same |
| US9365947B2 (en) | 2013-10-04 | 2016-06-14 | Invensas Corporation | Method for preparing low cost substrates |
-
1990
- 1990-03-20 JP JP6815390A patent/JPH03270193A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06302940A (en) * | 1993-04-12 | 1994-10-28 | Nec Corp | Formation of solder film |
| US7546681B2 (en) | 1999-10-12 | 2009-06-16 | Tessera Interconnect Materials, Inc. | Manufacturing method for wiring circuit substrate |
| US7721422B2 (en) | 1999-10-12 | 2010-05-25 | Tessera Interconnect Materials, Inc. | Methods of making microelectronic assemblies |
| US8162152B2 (en) | 2005-10-04 | 2012-04-24 | Jms Co., Ltd. | Blood filter device and method of manufacturing the same |
| US9365947B2 (en) | 2013-10-04 | 2016-06-14 | Invensas Corporation | Method for preparing low cost substrates |
| US10283484B2 (en) | 2013-10-04 | 2019-05-07 | Invensas Corporation | Low cost substrates |
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