JPS62214690A - Electroplating of ceramic board for electronic parts - Google Patents
Electroplating of ceramic board for electronic partsInfo
- Publication number
- JPS62214690A JPS62214690A JP5681586A JP5681586A JPS62214690A JP S62214690 A JPS62214690 A JP S62214690A JP 5681586 A JP5681586 A JP 5681586A JP 5681586 A JP5681586 A JP 5681586A JP S62214690 A JPS62214690 A JP S62214690A
- Authority
- JP
- Japan
- Prior art keywords
- electroplating
- coating layer
- wiring pattern
- plating
- conductive coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009713 electroplating Methods 0.000 title claims description 22
- 239000000919 ceramic Substances 0.000 title claims description 9
- 238000007747 plating Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000001556 precipitation Methods 0.000 claims description 2
- 239000011247 coating layer Substances 0.000 description 20
- 239000010410 layer Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、′電子部品用セラミック基板の電気めっき方
法に係り、電気めっきの陰極電極となるべき外部端子と
接続のない表面配線パターンにも電気めっきを可能にす
る好適な電気めっき方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for electroplating ceramic substrates for electronic components, and is applicable to surface wiring patterns that are not connected to external terminals that are to serve as cathode electrodes for electroplating. The present invention relates to a suitable electroplating method that enables electroplating.
）〔従来の技術〕
従来、電気めっきの陰極電極となるべき外部端子と接続
のない表面配線パターンに電気めりぎを施そうとする場
合、特開昭５９−１５３８９１号公報に記載のように、
前記端子と接続のあるパターンを又は前記端子を導′ｆ
１１塗布層で連結しさらＫその上に絶縁材を被覆し露出
したパターンのみに所望の電気めっきヲ施していた。し
かしこの方法では。) [Prior Art] Conventionally, when attempting to perform electroplating on a surface wiring pattern that is not connected to an external terminal that is to serve as a cathode electrode for electroplating, a method as described in JP-A-59-153891 has been used. ,
A pattern connected to the terminal or a pattern connected to the terminal
They were connected by 11 coated layers, coated with an insulating material, and only the exposed patterns were electroplated in the desired manner. But with this method.
導体塗布層とパターンの間の接続抵抗大により所望の電
気めっきが得られない不良が生じる可能性があった。Due to the high connection resistance between the conductor coating layer and the pattern, there was a possibility that a defect would occur in which desired electroplating could not be obtained.
［発明が解決しようとする問題点〕
上記従来技術は、電気めっきのための陰極電極となる導
体塗布層と塗布層下の配線パターン間の接触抵抗と電気
めっきのつきまわりの関係について配慮がされておらず
、上記接触抵抗が大であると所望の電気めっきが析出し
ないという問題があった。[Problems to be Solved by the Invention] The above-mentioned prior art does not take into account the relationship between the contact resistance between the conductor coating layer, which serves as a cathode electrode for electroplating, and the wiring pattern under the coating layer, and the electroplating coverage. If the contact resistance is high, there is a problem that the desired electroplating will not be deposited.
本発明の目的は、上記接触抵抗の大小にかかわらず、所
望の電気めりき及膜を形成することにある。An object of the present invention is to form a desired electroplating film regardless of the magnitude of the contact resistance.
上記目的は、上記導体塗布層をわずかに露出させるよう
絶縁材を被覆することにより達成される。The above object is achieved by coating the conductor coating layer with an insulating material so as to slightly expose it.
電子部品用セラミック基板に外部端子を取付けた後、！
気めっきを施す場合この外部端子を電気めっきの陰極電
極として外部端子と接続のある表面配線パターンに電気
めっきを施すことができる、一方外部端子と接続のない
表面パターンに電気めっきを施す場合、外部端子と接続
のあるパターンとないパターンを導電塗布層で連結し、
さらにそ−の上に絶縁材を被覆し、めっきし導電塗布層
と絶縁材を除去する方法があるが、この方法では、導電
塗布層と表面配線パターンの接続抵抗が太きいと、外部
端子と接続のないパターンに電気めっきが析出しない。After attaching external terminals to the ceramic substrate for electronic components!
When applying air plating, this external terminal can be used as a cathode electrode for electroplating, and electroplating can be applied to a surface wiring pattern that is connected to an external terminal.On the other hand, when electroplating is applied to a surface wiring pattern that is not connected to an external terminal, Patterns with and without terminal connections are connected with a conductive coating layer,
There is a method in which an insulating material is coated on top of the conductive coating layer and the insulating material is removed by plating. However, with this method, if the connection resistance between the conductive coating layer and the surface wiring pattern is high, the external terminal No electroplating deposits on patterns with no connections.
本発明では上記導電塗布層７０表面よりわずかに露出さ
せることにより、その部分に電気めっきが析出し、その
めっき膜が表面配線パターンと接続されることにより、
導電塗布層と配線パターンの接続抵抗が大きくても所望
のめつき膜を形成できる。In the present invention, by slightly exposing the surface of the conductive coating layer 70, electroplating is deposited on that portion, and the plating film is connected to the surface wiring pattern.
A desired plating film can be formed even if the connection resistance between the conductive coating layer and the wiring pattern is high.
以下１本発明の一実施例を第１図、第２図および第３図
により説明する。An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.
第１図は、メタライズ印刷を行った後、積層焼Ｍを行な
うことにより所望の表面配線パター°ン２を有するセラ
ミック基板の外部端子取付はバ・・ド３に外部端子４を
接続し１表面配線パターンを導ｔａ布層５により電気ｕ
、Ｗされたところである。Figure 1 shows that external terminals can be attached to a ceramic substrate having a desired surface wiring pattern 2 by performing lamination firing M after metallization printing. The wiring pattern is electrically connected by the conductive cloth layer 5.
, W has just been done.
この表面配線パターンは他の装賃１例えば半導体チνブ
キャリャーと接続するためのものである。This surface wiring pattern is for connection to another component 1, such as a semiconductor chip carrier.
また導電塗布層はフェノール樹脂に銀粉を分散混合して
形成され、６０υ２０分のベーク処理を施しである。The conductive coating layer was formed by dispersing and mixing silver powder in phenolic resin, and was subjected to a baking process of 60 υ for 20 minutes.
第２図はセラミック基板上の表面配線パターンの被めっ
き部を露出させるよう、また上記導に塗布ＩＣＹわずか
に露出させるよう（導電塗布層露出部７）絶縁材層６馨
被覆した状態の平面図及び断面図である。絶縁材層６は
上記導体塗布層と同時剥離除去可能なめつきレジストを
選べばよい。Figure 2 is a plan view of a state in which the insulating material layer 6 is coated so as to expose the plated portion of the surface wiring pattern on the ceramic substrate and to slightly expose the coated ICY (conductive coating layer exposed portion 7). and a cross-sectional view. For the insulating material layer 6, a plating resist that can be peeled off and removed simultaneously with the conductor coating layer may be selected.
第３図は、第２図示のセラミ−ｌり基板に電気めりき法
で１表面配線パターンに所望のめっき層８を形成した鎌
、めっきレジスタ及び導電塗布層を導電塗布層７０部分
を除きたとえはりａ口上ン等の有機溶剤を用いて洗浄除
去した後、導電塗布層７０表面に析出しためっき嘆をホ
ーニング、たとえばサンドブラストにより除去した状態
の平面図及び断面図である。本発明によれば、′１気め
っきの陰極電極である外部端子と接続のないセラミ・ツ
ク基板の表面配線パターンへの電気めっき？可能にした
。FIG. 3 shows an example of a sickle, a plated resistor, and a conductive coating layer on which a desired plating layer 8 is formed on one surface wiring pattern by electroplating on the ceramic substrate shown in FIG. 2, excluding the conductive coating layer 70. FIG. 7 is a plan view and a cross-sectional view of a state in which plating deposits deposited on the surface of the conductive coating layer 70 are removed by honing, for example, sandblasting, after the conductive coating layer 70 has been washed and removed using an organic solvent such as an abrasive powder. According to the present invention, electroplating is applied to the surface wiring pattern of a ceramic substrate that is not connected to the external terminal, which is the cathode electrode of plating. made possible.
〔発明の効果］
本発明によれば、′１を気めっきの陰極電極となる導電
塗布層をわずかに露出させることにより、導電塗布層と
披めっきパターンとの接続抵抗が高くても所望のめっき
膜が得られ１通常２０チ出ていためっき不析出不良が０
％に低減できた。[Effects of the Invention] According to the present invention, by slightly exposing the conductive coating layer '1 which becomes the cathode electrode for plating, the desired plating can be achieved even if the connection resistance between the conductive coating layer and the plating pattern is high. A film was obtained and the number of plating non-precipitation defects, which were normally 20, was 0.
%.
第１図〜第３図は本発明の一実施例の工程を示す図であ
る。
１・・・セラミック基板、２・・・表面配線パターン。
３・・・外部端子取付バー・ト、４・・・外部端子、５
・・・導電塗布層、６・・・絶縁材層、７・・・導電塗
布層露出部。
８・・・めっき層〇1 to 3 are diagrams showing the steps of an embodiment of the present invention. 1...Ceramic board, 2...Surface wiring pattern. 3... External terminal mounting bar, 4... External terminal, 5
... Conductive coating layer, 6... Insulating material layer, 7... Conductive coating layer exposed portion. 8... Plating layer 〇
Claims (1)
表面配線パターンに電気めっきを施す場合、上記端子と
接続のあるパターンと剥離除去可能な導電ペーストで電
気結線し、その導電ペーストにめっきが析出しないよう
絶縁材を被覆する方法において、パターンとの結線の一
部の導電ペーストを露出させてめっきを施す電子部品用
セラミック基板の電気めっき方法。1. When electroplating is applied to a surface wiring pattern that is not connected to an external terminal that will serve as a cathode electrode for electroplating, the pattern that is connected to the terminal is electrically connected with a conductive paste that can be peeled off, and the plating is applied to the conductive paste. An electroplating method for ceramic substrates for electronic components, in which a part of the conductive paste connected to the pattern is exposed and plated, in a method of coating insulating material to prevent precipitation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61056815A JPH0744328B2 (en) | 1986-03-17 | 1986-03-17 | Electroplating method for electronic component substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61056815A JPH0744328B2 (en) | 1986-03-17 | 1986-03-17 | Electroplating method for electronic component substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62214690A true JPS62214690A (en) | 1987-09-21 |
| JPH0744328B2 JPH0744328B2 (en) | 1995-05-15 |
Family
ID=13037872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61056815A Expired - Lifetime JPH0744328B2 (en) | 1986-03-17 | 1986-03-17 | Electroplating method for electronic component substrates |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744328B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103046031A (en) * | 2012-12-11 | 2013-04-17 | 胜宏科技（惠州）股份有限公司 | Method for chemically gold-plating circuit board |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3357875B1 (en) * | 2001-06-29 | 2002-12-16 | 株式会社リョウワ | Electroplating method and method for manufacturing printed wiring board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4833553A (en) * | 1971-09-01 | 1973-05-11 |
-
1986
- 1986-03-17 JP JP61056815A patent/JPH0744328B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4833553A (en) * | 1971-09-01 | 1973-05-11 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103046031A (en) * | 2012-12-11 | 2013-04-17 | 胜宏科技（惠州）股份有限公司 | Method for chemically gold-plating circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744328B2 (en) | 1995-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3469686B2 (en) | Method of depositing solder on printed circuit board and printed circuit board | |
| US4581301A (en) | Additive adhesive based process for the manufacture of printed circuit boards | |
| US4404237A (en) | Fabrication of electrical conductor by replacement of metallic powder in polymer with more noble metal | |
| JPS63177496A (en) | Metallized board and manufacture of the same | |
| US6132588A (en) | Method for plating independent conductor circuit | |
| US4963389A (en) | Method for producing hybrid integrated circuit substrate | |
| JPS62214690A (en) | Electroplating of ceramic board for electronic parts | |
| US3554876A (en) | Process for etching and electro plating a printed circuit | |
| US4898805A (en) | Method for fabricating hybrid integrated circuit | |
| JPS62281396A (en) | Method of metallizing conductive paste circuit | |
| JP3189741B2 (en) | Plating method for independent conductor circuit | |
| JP3405640B2 (en) | Plating method for independent circuit | |
| JPH10284814A (en) | Circuit pattern and its formation | |
| JP6738690B2 (en) | Ceramic wiring board manufacturing method | |
| JP3950950B2 (en) | Manufacturing method of ceramic wiring board | |
| WO1998019858A1 (en) | Circuit comprising microstrip conductor and method for making the same | |
| JPS6031116B2 (en) | Electric wiring circuit board and its manufacturing method | |
| JPS6182493A (en) | Manufacture of ceramic circuit board | |
| JP3439779B2 (en) | Manufacturing method of printed wiring board and printed wiring board | |
| JPS5892293A (en) | Circuit board and method of producing same | |
| JP2734184B2 (en) | TAB tape carrier | |
| JPH01140695A (en) | Manufacture of electronic circuit component | |
| JPH1112789A (en) | Method for plating independent conductor circuit | |
| JPH0465024A (en) | Jumper chip | |
| JPS60170247A (en) | Electrically plating method of semiconductor package |