JPS60170247A - Electrically plating method of semiconductor package - Google Patents
Electrically plating method of semiconductor packageInfo
- Publication number
- JPS60170247A JPS60170247A JP2506384A JP2506384A JPS60170247A JP S60170247 A JPS60170247 A JP S60170247A JP 2506384 A JP2506384 A JP 2506384A JP 2506384 A JP2506384 A JP 2506384A JP S60170247 A JPS60170247 A JP S60170247A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- paste
- conductive
- electroplating
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000007747 plating Methods 0.000 title abstract description 34
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 238000009713 electroplating Methods 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000001556 precipitation Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000001376 precipitating effect Effects 0.000 description 2
- 235000001270 Allium sibiricum Nutrition 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000013035 low temperature curing Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体用セラミックパッケーシノ電気メッキ
方法に係り、外部端子と導通のない表面配線パターンに
もメッキを可能にする好適な電気メツキ法に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an electroplating method for ceramic packages for semiconductors, and more particularly, to a suitable electroplating method that enables plating even surface wiring patterns that have no electrical continuity with external terminals. .
外部端子と導通のない表面配線パターンを有するセラミ
ックパックージの電気メッキにおいて、従来は、外部端
子と導通のない表面配線パターンはあらかじめパターン
形成の際外部端子と導通のある配線パターンと接続させ
、電気メッキを施した後レーザ等により接続されたパタ
ーン部をカットする方法を取っていたが、パターンカッ
ト作業の、能率が悪く、問題であった。Conventionally, in electroplating of a ceramic package that has a surface wiring pattern that has no electrical continuity with an external terminal, the surface wiring pattern that has no electrical continuity with the external terminal is connected in advance to a wiring pattern that has electrical continuity with the external terminal during pattern formation. The conventional method used was to cut the connected pattern portions using a laser or the like after electroplating, but the pattern cutting process was inefficient and problematic.
本発明の目的は、外部端子と導通のない表面配線パター
ン上にも電気メツキ皮膜を形成可能にした電気メツキ方
法を提供することにある。An object of the present invention is to provide an electroplating method that makes it possible to form an electroplating film even on a surface wiring pattern that is not electrically connected to an external terminal.
リード付後電気メッキを行なう場合、外部端子としての
リードをメッキ電極として表面配線パターン上にメッキ
を施すのが一般的な方法であるが、リードに導通の無い
メッキ必要部分が有る場合メツキネ可能とな、る。この
ような場合メッキの為の配ｆｉ！７ｗ基板内に設はメッ
キ后基板の一部を切断除去する方法があるが、しかしこ
の配線を設けることが出来ない場合が多くメッキするこ
とか不可能となる。本発明では、電気メッキを行なう前
に外部端子と導通のないメッキ必要部分と外部端子と導
通のある部分とを導電性ペーストにより接続させ、外部
端子と導通のない部分にもメッキを施すことが出来、メ
ッキ後導電性ペーストを除去すればよい。しかし本方法
では導電性ペースト上にもメッキが析出し、ペーストの
除去が困蛭なことおよび余分なＡｕが析出することより
Ａｕ代の浪費に結がるがペースト上に更に絶縁体を施す
ことにより除去が容易となりまた余分なメッキが析出し
ないことより好適な電気メツキ方法である。When performing electroplating after attaching leads, the general method is to use the leads as external terminals as plating electrodes and plate them on the surface wiring pattern, but if there are parts of the leads that require plating that are not conductive, it is possible to do electroplating. Become. In such cases, it is necessary to arrange for plating! There is a method of cutting and removing a part of the board after plating it in the 7W board, but in many cases it is not possible to provide this wiring, making plating impossible. In the present invention, before electroplating, it is possible to connect the parts requiring plating that are not electrically conductive to the external terminals and the parts that are electrically conductive to the external terminals using conductive paste, and to apply plating to the parts that are not electrically conductive to the external terminals. All you have to do is remove the conductive paste after plating. However, in this method, plating is deposited on the conductive paste as well, making it difficult to remove the paste, and extra Au deposits, resulting in a waste of Au money. This electroplating method is more suitable because removal is easier and no excess plating is deposited.
以下、本発明の実施態様を説明する。第１図は半導体パ
ッケージの電気メツキ前の状態を示すもので、セラミッ
ク多層基板３にリードフレーム／ガロウ付されており、
ロウ付バッド２は基板の内層配線にて一部の表面配線４
と接続しているため、この部分にはリードフレームを介
してメッキの導通が取れ、メッキ可能であるが、リード
フレームに内部接続して−いない表面配線５があるとメ
ツキネ可能となる。本問題を改良する実施例を述べる。Embodiments of the present invention will be described below. FIG. 1 shows the state of the semiconductor package before electroplating, in which a lead frame/gallow is attached to a ceramic multilayer substrate 3.
The soldered pad 2 is part of the surface wiring 4 in the inner layer wiring of the board.
Since this part is connected to the lead frame, plating is established through the lead frame and plating is possible, but if there is surface wiring 5 that is not internally connected to the lead frame, plating is possible. An example that improves this problem will be described.
実施例１ （第２図参照）電気メツキ前にり一ドフレー
ム１と接続のない表面配線５と接続のある表面配線４と
の導通な図るため、導電性ペースト、例えば低温硬化型
のＡｇペーストもしくはＣｕペーストを６のようにスク
リーン印刷もしくは刷毛で塗布し、接続した後、７０〜
８０°Ｃで乾燥する。その後、ペースト上に絶縁体とし
てスクリーン印刷用のメツキレシストをスクリーン印刷
もしくは刷毛でペーストと同様に塗布。Embodiment 1 (See Figure 2) Before electroplating, conductive paste, such as low-temperature curing Ag paste, was applied to ensure electrical continuity between the board frame 1, the unconnected surface wiring 5, and the connected surface wiring 4. Alternatively, apply Cu paste by screen printing or brushing as shown in step 6, connect it, and then
Dry at 80°C. Then, apply Metsuki Resist for screen printing as an insulator on the paste using screen printing or a brush in the same way as the paste.
乾燥を行なう。メツキレシストを塗布する目的はペース
トのみの場合、ペースト上にもメッキが析出し、メッキ
後のペースト剥離が困難でしかも高価なＡｕがペースト
上に析出しないよう行なうものである。しかる後、メッ
キの前処理を経て電気Ｎｉメッキ、電気Ａｕメッキを行
なう。メッキ後、トリクレン（８０〜９０℃の液温）中
に浸漬し、超音波をかけ、メツキレシスト、導電性ペー
ストの剥離を行なう。Dry. The purpose of coating the metal resist is to prevent the plating from precipitating on the paste when only the paste is used, making it difficult to peel off the paste after plating, and preventing the expensive Au from precipitating on the paste. Thereafter, electroplating of Ni and Au is performed after pretreatment for plating. After plating, the plate is immersed in trichloride (liquid temperature of 80 to 90°C) and ultrasonic waves are applied to peel off the metal resist and conductive paste.
この方法により、リードフレームと接続のない表面配線
上にもメッキが可能となる。This method allows plating even on surface wiring that is not connected to the lead frame.
実施例２は実施例１と同様導電性ペーストを塗布、乾燥
した後、絶縁体としてポリエステルチーブをペースト上
に粘着させ、電気メッキ後テープを剥した後、実施例１
と同様にトリクレンに゛て導電性ペーストの剥離を行う
。この方法でもリードフレームと接続のない表面配線上
にもメンキが可能である。Example 2 is similar to Example 1, in which a conductive paste is applied, dried, a polyester chive is adhered to the paste as an insulator, and after electroplating, the tape is peeled off.
Peel off the conductive paste using trichloride in the same manner as above. With this method, it is also possible to patch surface wiring that is not connected to the lead frame.
以上に詳述したように、本発明による方法にて電気メッ
キを行なうことにより、外部端子と接続していないメッ
キ必要な表面配線ヘメッキすることが可能となる。また
本方法は特別な装置等必要とせず容易に行なうことが出
来ると同時に、一般的な方法で行なわれているメッキの
方法即ちメッキの為の配線を基板内に設はメッキ后基板
の一部を切断除去する方法において、高密度配線パター
ンではメッキつための配線な設けることが出来ないもの
に適用可能となる。As described in detail above, by performing electroplating using the method according to the present invention, it becomes possible to plate surface wiring that is not connected to an external terminal and that requires plating. In addition, this method can be easily performed without requiring any special equipment, and at the same time, it does not require the use of a general plating method, i.e., the wiring for plating is placed inside the board, but only a part of the board is plated. This method of cutting and removing can be applied to high-density wiring patterns where wiring for plating cannot be provided.
第１図はセラミックパンケージの平面図及び側面図、第
２図は本発明の一実施例を示す平面図である。
１・・・リードフレーム、２・・・リード付ハツト、５
・・・セラミック多層基板、
４・・・リードと接続がある表面配線、５・・・リード
と接続がない表面配Ｍ。
第１図
（グ）
第２輿
（ｂ）FIG. 1 is a plan view and a side view of a ceramic pan cage, and FIG. 2 is a plan view showing an embodiment of the present invention. 1...Lead frame, 2...Leaded hat, 5
...Ceramic multilayer board, 4...Surface wiring with leads and connections, 5...Surface wiring M without leads and connections. Figure 1 (g) 2nd palanquin (b)
Claims (1)
外部端子と電気的導通のある部分に、外部端子と電気的
に導通のない部分を導電性ペーストを塗布して電気的導
通をはかり、その上に絶縁体を施して電気メッキを行な
い、電気メツキ後、上記絶縁体および導電性ペーストを
除去することを特徴とする半導体パッケージの電気メツ
キ方法。1. In the electroplating method for semiconductor packages,
Apply conductive paste to the parts that are electrically conductive to the external terminals and to the parts that are not electrically conductive to the external terminals to establish electrical continuity, then apply an insulator on top of that and perform electroplating. A method for electroplating a semiconductor package, comprising: thereafter removing the insulator and the conductive paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2506384A JPS60170247A (en) | 1984-02-15 | 1984-02-15 | Electrically plating method of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2506384A JPS60170247A (en) | 1984-02-15 | 1984-02-15 | Electrically plating method of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60170247A true JPS60170247A (en) | 1985-09-03 |
Family
ID=12155456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2506384A Pending JPS60170247A (en) | 1984-02-15 | 1984-02-15 | Electrically plating method of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60170247A (en) |
-
1984
- 1984-02-15 JP JP2506384A patent/JPS60170247A/en active Pending
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