JPS6180452A - Vector processor - Google Patents

Abstract

PURPOSE:To obtain a vector processor which is most suitable to the logical simulation and picture processing by executing at a high speed a logical operation which is expressed in the combination of logical operations to a specific field of the data to be operated. CONSTITUTION:When a processor is started, a controller 101 performs a prescribed preparation and then indicates the start to a vector processor 102. A control circuit 103 reads out a vector instruction stored in a main memory 100. Based on this vector instruction, it is checked whether the necessary resources can be used or not. Then the vector instruction is executed only when the necessary resources can all be used. The vector processing operation is carried out in two steps, that is, the regulation of the vector operator processing function done by the preparatory processing before the start of the processor 102 and the designation of a computing element in a vector instruction mode. The circuit 103 in the processor 102 sends the information on the end of the vector processing to the controller 101 when a series of vector processings are through. The data on the logical simulation and the picture processing are processed by repeating said preparatory processing are vector processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processing device, and particularly to a vector processing device suitable for image processing, logic simulation, and the like.

[Background of the invention]

Conventionally, various vector processing devices have been proposed to perform high-speed vector processing, which frequently occurs in scientific and technical calculations. One of the vector processing devices is a vector processing device that includes a plurality of vector arithmetic units, a vector register, and a plurality of queuers that transfer data between the vector register and the main memory (CRAY-1 computer system, " General-purpose large computer JP, 283~
295, Nikkei McGraw-Hill, 1982).

In such a vector processing device, the operand data in the main memory is loaded into a vector register by the quester, and then sent to the vector arithmetic unit according to the specification of the vector instruction, processed, and stored in the vector register. . The data on this vector register is subsequently decoded if a vector instruction specifies data processing.

The data is sent to the vector arithmetic unit and processed without going through the main memory. In this way, data processing specified by a series of vector instructions is performed via vector registers, which have faster access times than main memory, without going through main memory. It has the advantage of ensuring the data transfer capacity necessary for calculations even if the design is

When a vector processing device is applied to large-scale data processing other than scientific and technical calculations, such as logic simulation of electronic circuits and image processing, high-speed vector processing is possible for logical operations via vector registers. However, the data for logical simulation and image processing is different from scientific calculations.

There are many logical operations that are expressed by combinations of logical operations on specific fields of data to be operated on, and for these types of operations, current vector processing devices carry out the following processing to perform the desired logical operation.

(1) Match the relative positions between specific fields of operand data.

(2) Perform logical operations between specific fields of operand data.

(3) Overwrite the operation result obtained in (2) in the specific field of the operand data.

(4) The above processes (1) to (3) can be repeated as many times as necessary.

Processes (1) to (4) above can be performed at a certain level of high-speed processing using current vector processing devices and using a chaining function. However, with the processing of current vector processing devices, it is impossible to reduce the number of accesses to the vector registers required between the operations (1) to (4) above to almost zero. In a process that uses one vector arithmetic unit for complex data processing, if the processing becomes complex, there will be a shortage of arithmetic units, and this will cause chaining to become impossible. This causes a significant decrease in processing speed.

In this way, current vector processing devices are not required for logical operations expressed by combinations of logical operations on specific fields of operand data, which often appear in logic SIMILE-9321 image processing. Unable to demonstrate sufficient processing performance.

[Purpose of the invention]

An object of the present invention is to realize a vector arithmetic unit that can quickly execute any logical operation expressed by a combination of logical operations on a specific field of operand data, and to provide a vector processing device that is optimal for logic simulation and image processing. It's about doing.

[Summary of the invention]

A logical operation expressed by a combination of logical operations on a specific field of data to be operated on is hereinafter referred to as a combinational logical operation. The conditions necessary for a vector arithmetic unit that processes this combinational logic operation at high speed are as follows.

(1) Means for specifying combinatorial logic operations.

(2) Multiple computing units that perform basic logical operations.

(3) A logic circuit that writes the operation result to any field of the operand data.

The logical operation operation regulation means (1) can be easily realized by providing storage means for holding processing operation instructions corresponding to a plurality of arithmetic units.

Regarding (2), the connection relationship between a plurality of arithmetic units becomes an important issue in terms of function and performance. When multiple calculation units are connected in parallel, calculations are performed on multiple fields at the same time.
In terms of performance, it is the most preferable arithmetic unit. However, in this case, it is difficult to realize the process of writing the operation result in (3) into a specific field, especially when there is overlap between fields or empty areas.

When multiple arithmetic units are connected in series, operations are performed serially on multiple fields. However, by operating the vector arithmetic unit under pipeline control, it is possible to design the vector arithmetic unit so as not to cause a significant drop in performance compared to parallel-coupled arithmetic units. Furthermore, by performing the process of writing the calculation result in (3) serially in a manner compatible with basic arithmetic units, it is possible to reduce the process to writing a single calculation result to an arbitrary field, simplifying the logic. Ru. Further, by arranging the arithmetic units in series, it becomes possible to perform the next logical operation using the operation result of the previous stage. This indicates that a high-order combinatorial logical operation expressed by a combination of one combinatorial logical operation (hereinafter this type of logical operation will be referred to as a cOmplex logical operation) can also be processed by serially coupled arithmetic units. Therefore, in terms of function and performance, vector arithmetic units with a configuration in which logic arithmetic units are connected in series and each stage is provided with a means for writing the arithmetic result to an arbitrary field of the data to be operated on are suitable for logic simulation and image processing. It is considered to be a suitable arithmetic unit for The present invention realizes such a vector arithmetic unit.

The data processing that appears in logic simulations is characterized by multiple combinatorial logic operations. Therefore, it is impossible to design a dedicated vector arithmetic unit for each combinatorial logical operation due to hardware limitations. Therefore, it is necessary to design a vector calculator that can be applied to any type of combinatorial logic operation, and a means is needed to dynamically specify the processing operation of the vector calculator while performing logic simulation processing. becomes. In order to realize this means, 1 the present invention considers a control device that controls a vector processing device, and uses the control device to specify the processing operations of a logical arithmetic unit and a calculation result writing circuit, which are components of a vector arithmetic unit. A control information write bus is provided so that control information can be written to the storage means, and the control information write operation can be performed by a command from a control device of the vector processing device. This allows the combinatorial logic operation or con+plex logic necessary for the first step simulation process to be performed during the execution of the logic simulation.
The vector arithmetic unit required to execute the l operation can be conceptually generated, and high-speed logic simulation becomes possible.

[Embodiments of the invention]

FIG. 1 shows a schematic block diagram of a vector processing device according to the present invention. In FIG. 1, 100 is a main storage device, and 102 is a vector processing device.

101 is a control device for controlling the vector processing device. 103 is a vector processing device management circuit, and memory requester 104 . It manages activation and termination processing of the vector register 106 and switching circuits 105 and 107 that switch data buses for performing read/write operations of the vector register 106.

Reference numeral 109 denotes a logic operation unit capable of performing an arbitrary logic operation on a specific field of data to be operated, and reference numeral 11O indicates a storage circuit that holds information that defines the processing of the logic operation unit 109. The memory circuit 110 and the logic operation unit 109 are each connected in series to form a vector operation unit 108.

In FIG. 1, for convenience, memory requester 104, vector register 106 . Although one vector arithmetic unit 108 and the like is shown, there are generally a plurality of these. In addition, the logical operator 1 in the vector operator 108
09. Although the number of memory circuits 110 is also three, it is not necessary to limit it to this.

When the processing device is started, the control device 101 reads instructions related to the control of the vector processing device 102 from the main storage device lOO. In this command.

It includes instructions that define the processing operations of the vector arithmetic unit 108. When the instruction is decoded by the control device 101, the control device lot loads the vector processing device management circuit 1.
03, the storage circuit 11 in the vector arithmetic unit 108
Write logic operator control information to 0. vector calculator 10
Each of the plurality of logic operators 109 in the vector calculator 108 is assigned a unique number, and the control device 101 sends out the control information in correspondence with the unique number to set the control information. Any logical operation unit 109 can be caused to perform a unique logical operation specified by the instruction.

The following describes the processing that precedes the vector processing described above.

This will be called setup processing.

Subsequently, when the control device 101 instructs the vector processing device 102 to start up, the management circuit 103 reads the vector instruction stored in the main memory bag aioo, and executes the necessary memory requester and vector register according to the information of the instruction. , checks whether vector arithmetic units (these are collectively referred to as resources) are available for use, and executes the vector instruction only when all requested resources are available. At this time, the vector processing operation is performed in two steps: defining the processing function of the vector arithmetic unit by a set-up process before starting up the vector processing device 1-2, and specifying the arithmetic unit in the vector instruction. After a series of vector processing is completed, the management circuit 103 in the vector processing device 102 sends vector processing completion information to the control device 101.

Data processing related to logic simulation and image processing is performed by repeating the above setup processing and vector processing.

FIG. 2 is a block diagram of the logical arithmetic unit 109 of FIG. 1 and the storage circuit 110 holding its control information.

During setup processing, logic operation unit control information is stored in memory circuit 1.
Set to 10. The memory circuit 110 has three fields 201, 202, 203. Each field holds shift information of operand data, logical operation information, and information regarding storage of results.

During vector processing, once the operand data is sent to the vector calculator, the operand data is stored in registers 204 and 205. In order to perform logical operations between specific fields of operand data, it is necessary to match mutual bit positions. For this reason, the shifters 206 and 2
Shift processing is performed in step 07. The shift amounts of shifters 206 and 207 are determined from shift information set in field 201 of storage circuit 110 during setup processing.

After the shift processing, the memory circuit 110 is
The logical operations defined in the field 202 are performed here.Logical operations are the logical operations necessary for logic simulation and image processing, i.e., basic logical operations such as logical sum, logical product, exclusive logical sum, inversion, and so on. This refers to logical operations such as logical operations, and does not include logical operations such as comparison. Logical operation result is in register 2
09 and after timing alignment, it becomes an input to the merge circuit 210 together with the operand data held in the registers 204 and 205, and the operation result is stored in a specific field of the operand data according to the field 203 of the storage circuit 110. is written. The output of the merge circuit 210 is 1
If there is a logical operator in the next stage, 2 paths 211, 21
2, and in the final stage arithmetic unit that does not exist, 1 pass 212
Only.

Therefore, when specifying the processing operation of the logic arithmetic unit at the final stage of the vector arithmetic unit, it is necessary to perform setup processing with this point in mind. The logic of the merge circuit 210 can be configured by shifters and selectors.

Figure 3 defines four 2-byte wide fields on an 8-byte vector register, and their four input signal values s, , s
, , s, , s, is a diagram showing a case where a conventional vector processing device and a vector processing device of the present invention perform a process of calculating the logical product of , s, , s. FIG. 3(a) shows a case where the conventional vector is a processing device.

FIG. 3(b) shows the case of the vector processing device of the present invention.

First, FIG. 3(a) will be explained. Input data 2
When the data is shifted to the left by bytes, the data in the S field is lost, and the rightmost 2-byte field is filled with 0. This shifted result is designated as 301b, and the data before shifting is designated as 301a.

Next, all 8 bytes of data 301a and 301b are ANDed, and the result is 3010. Here, unnecessary field data in the 5th stage is indicated by diagonal lines in the 6th and 3rd stage.
If you shift the data of 010 by 4 bytes to the left, it will shift 4 bytes from the right end.
There will be an O before the part time job. This is designated as 301d. Here again, fields unnecessary in the primary stage are logically ANDed of 8 bytes of 0th order 3010 and 301d shown by diagonal lines, and the result is 3018. The target Sl, S2, Sl, and S4 are obtained in the leftmost 2 bytes of this 3018.

Next, the case of FIG. 3(b) will be explained in relation to the configuration of FIG. 2. Here, it is assumed that the data width of the registers 204 and 205 in FIG. 2 is 8 bytes.

First, data 301A is loaded into registers 204 and 205. A register 204 is provided in 201 of the memory circuit 110.
Information that the data in the register 205 is not shifted (ie, shifted to the left by 0 bits) and information that the data in the register 205 is shifted to the left by 2 bytes are set up. At 202, an operation code for instructing a logical product is set up, and at 203, an instruction for writing the operation result onto the data in the registers 204 and 205 is set up. This memory circuit 11
When the calculation process specified by 0 is performed, the path 211.212
Both of the above data are the same as the data 3010 in FIG. 3(a).

The data on paths 211 and 212 are stored in input registers 204 and 205 of the next-stage logical arithmetic units connected in series. To distinguish this register from the previous one, 204
' , 205'. Similarly, the storage circuit for the logical operation unit of the first stage is assumed to be 110'. The information in the storage circuit 110' for the logical operation unit at the next stage includes information instructing a 0-bit shift for the data in the register 204' and a 4-byte left shift for the data in the register 205' in 201';' is information indicating logical product, 203
contains information for displaying the calculation results on the data in the registers 204' and 205'. Memory circuit 110'
If you perform the logical operation specified by .

301e in FIG. 3(a) is on the path 211 or 212.
The same data appears.

That is, by using the series-coupled logic arithmetic units of the present invention, the desired arithmetic result can be obtained at the output of the second stage. If the arithmetic units are composed of three or more stages, a ``do nothing'' instruction may be set up for the arithmetic units in the third and subsequent stages.

Comparing the performance of the processing in FIG. 3(a) and FIG. 3(b), the results are as follows.

Processing in FIG. 3(a); ■ VLD VRo, 301 a (loads data 301a to vector register VRO) ■ VSHIFT VRI, VRo, 2B (shifts left by 2B) ■ VAND VR2, VRl, VRO (logical (takes the product) ■ VSHIFT VR3, VR2, 4B (shifts 4B to the left) ■ VAND VR4, VR2, VR3 (takes the logical product) +li+ VSTD VR4, 301e
(Storing results) Processing in Figure 3 (b); ■ VLD VRo, 301A+z VL
D VRl, 301A (vector register V
Load the data of 301A into R0, 1) @ VMACROL VR2, VRO, VRI (perform macro-logical operations) tl VSTD Time when performing the processing in Figure 3 (a) above with a vector processing device having VR2, 301e FIG. 4(b) is a time chart in the case of the present invention shown in FIG. 3(b). , where n indicates the number of vector elements. From FIG. 4, the present invention is three times faster than the conventional method.

Furthermore, from the control circuit within the vector processing device, the number of logical arithmetic units appears to be one, which is effective in reducing the amount of hardware in the control circuit. These are summarized as shown in Figure 5.

〔Effect of the invention〕

According to the present invention, any logical operation can be performed on a specific field on a vector register, and by combining these basic logical operations, one macro logical operation can be performed by one vector operator, so that complex logical operations can be performed. It has a significant performance advantage in data processing that requires a large number of operations, such as logic simulation of electronic circuits and image processing.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a vector processing device of the present invention;
Figure 2 is a detailed diagram of the vector arithmetic unit in Figure 1;
The figure is a comparison diagram of the processing of the conventional vector processing device and the vector processing device of the present invention, FIG. 4 is a timing diagram of the conventional device and the present invention device, and FIG. 5 is a performance comparison diagram. 100...Main storage device 1. 101... Vector processing device control device, 102... Vector processing device, 103... Vector processing device management circuit, 104
...Memory requester, 105,107...Switch song circuit, 106...Vector register. 10B...Vector arithmetic unit, 109...Logic arithmetic unit, 110...Storage circuit. Figure 3 (OL) (!r-)

Claims (1)

[Claims] (1) A requester that transfers data between the main memory device, a vector register, and the main memory device and the vector register, performs vector arithmetic processing on the vector data received from the vector register, and sends the result to the vector register. In a vector processing device equipped with a vector arithmetic unit, the logical arithmetic unit has the function of executing an arbitrary logical operation on a specific field of operand data and storing the result in an arbitrary field of the operand data. 1. A vector processing device comprising: a vector computing unit configured by connecting a plurality of logic computing units in series; and means for controlling processing operations of said logical computing unit.