JPS6177940A - Rise control method for processor - Google Patents

Abstract

PURPOSE:To improve greatly the debug efficiency by applying the outputs of a reset switch and a debug switch to a pulse generator after inverting them by an inverter respectively to obtain a reset output and at the same time applying a debug signal to a gate circuit. CONSTITUTION:The output of a reset switch 6 is inverted by an inverter 24 and supplied to an OR gate 25. While the output of a debug-only reset switch 7 is inverted by an inverter 23 and supplied to gates 25 and 28. When either one of both switches 6 and 7 is turned on, an OR gate signal 30 is also turned on. Then the signal 30 is supplied to a pulse generator 26 for a fixed period of time and then delivered 27. While this pulse is kept ON, a processor 11 resets the connection with an internal bus and a bus 14 to put the input signal group of the gate 28 on a signal 29 and processes the contents of the signal group as the program address. Thus the reset and debug programs are executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a startup control method for a processing device that performs automatic diagnosis at startup.

[Background of the invention]

Conventionally, automatic diagnostic functions were often added to processing equipment to ensure system reliability.
The 5 processing unit operation manual states that when a hardware reset is applied, the main memory is checked. Also.

5alf-diagnosing minicomp
utar (MINI-MICRO3YSTEMS/J
Uly 1980), if you apply a hardware reset, the hard core section (including 32 bytes of RAM) will be reset.
Single -board co＋＊put with
It is stated that er) should be checked.

However, with advances in semiconductor technology, the capacity of memory has increased, and the speed of processors has slowed down in comparison.
There is a problem that the check time at startup is very long.1 For example, regarding checking the main memory,2 MI
It takes several seconds for a PS-sized processor to check a memory of 8 Mbytes (access width: 8 bytes), but when the memory is expanded to 32 Mbytes, it takes about 20 seconds.

There is no problem if the system startup frequency is about 71 days and about 20 seconds each time, but when debugging the system, it is necessary to start up the system many times, which poses a problem.

Furthermore, the PC-4001 USER'S MANUAL states that a memory test is performed upon activation by the operator. However, in this method, although it is not necessary to start the memory test during debugging, in order to guarantee the reliability of the system, the operator must start the memory test at the time of daily startup, which is cumbersome.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a tII startup method for a processing device with an automatic diagnosis function at startup, which is optimal for dealing with the increase in check time due to an increase in memory capacity.

[Embodiments of the invention]

1 The present invention will be described in detail below.6 FIG. 2 shows an example of the overall configuration of a processing device system which is the background of the present invention.The processing device Wt1 includes a display device such as a character display for the operator. 2 and an input device 3 from an operator such as a keyboard are connected. Also,
The processing device 1 has an auxiliary storage bag [4] and an operator panel 5, and the operator panel 5 has a reset switch 6 (
A debug-only reset switch 7 (also a push button type) is provided.

FIG. 3 shows the internal configuration of the processor 1.
1 reads and executes a program in the ROM 12 or main memory 13 via the system bus 14. Further, the processor 11 can read the contents of the power-on flag 18 via the same path 14 and the gate 15. Further, the processor 11 communicates with the display panel 2 for the operator and the input device 3 from the operator via the same path 14, the console input/output device connection structure 16, and the interface cable 8. The auxiliary storage connection mechanism 17 can be activated via the path 14, and the activated mechanism 17 transfers data between the auxiliary storage device 4 and the main memory 13.The output of the reset switch 6 is output to the processor. 11, and when the switch is on, the processor 11 resets each connection mechanism connected internally and to the system bus 14, and starts from a specific address A (for example, address 0) after a certain period of time. The address corresponds to the address in ROM12,
The processor 11 sequentially reads programs from the ROM 12 and executes them. The program started by this reset is hereinafter referred to as a reset program. The output of the reset switch 6 is also input to the power-on flag 18, and when the reset switch 6 is turned on, the flag is set to 0.
become. The output of the debug-only reset switch 7 is input to the processor 11, and when the switch is on, the processor 11 resets each connection mechanism connected to the internal and system bus 14, and after a certain period of time,
Furthermore, the address B (
For example, start from address 100). The address is RO
The processor 11 sequentially reads programs from the ROM 12 and executes them. The program started by this debug-only reset is hereinafter referred to as a debug-only reset program. The power restoration control unit 19 outputs a pulse for a certain period of time when power is restored to the processing device. This output is input to the processor 11 and performs a hardware reset and starts the reset program in the same way as when the reset switch 6 is turned on.The same output is also output to the power-on flag 18.
The power-on flag 18 is set to 1 when the power is restored.

Figure 4 shows the power-on flag 18. The detailed configuration of the power recovery control unit 19 is shown. At the time of power recovery, while charging the capacitor 21 through the resistor 22, the output of the power recovery control unit 19 becomes 1, and the power-on flag 18 is turned on. On the other hand, when the reset switch 6 is turned on, the power-on flag 18 is turned off.

FIG. 5 shows the detailed configuration of the reset input receiving section of the processor 11. The output of the reset switch 6 is connected to the inverter 24.
is inverted and input to the OR gate 25. The output of the debug-only reset switch 7 is inverted by an inverter 23 and input to an OR gate 25 and a gate 28. When either the reset switch 6 or the debug-only reset switch 7 is turned on, the OR gate output signal 30 is turned on. This signal is input to a pulse generator 26 that generates a pulse of a fixed duration, and when the signal 30 is turned on, a pulse is output to the output 27 of the generator. While this pulse is on, the processor 11 resets each connection mechanism connected to the internal and system bus 14, and when it is off, the processor 11 turns on the gate 28 and superimposes the input signal group of the gate 28 on the signal 29. , the contents of signal 29 are processed as a program address. The width of the pulse 27 is sufficiently short compared to the time the operator continues to press the switch, so when the operator presses the reset switch 6, the processor 11
The program address taken in by the processor 11 is the address where the signal 31 is 0, and when the debug-only reset switch 7 is pressed, the program address taken in by the processor 11 is the address where the signal 31 is 1. In this way, when starting with the reset switch 6, address A is used, and when starting with the debug-only reset switch 7, address B is used.
Each program is executed.

FIG. 1(a) shows a flowchart of a reset program. This program starts from address A and is stored in the ROM.
It is stored in 12. When the reset switch 6 of the processing device is pressed, the hardware of the processing device is reset and then linked to the reset program. This program first determines power-on flag 18 (a flag indicating that the reset program has been activated by power-on), and if the flag is 1, it clears all areas of main memory to zero and releases the parity state. do.

Next, regardless of the contents of the power-on flag 18, the power-on flag 18 is determined again in the primary stage where the processor peripheral self-diagnosis and main memory check are performed, and if the flag is 1, the IPL (program (loading from auxiliary storage) and start. On the other hand, when the flag is 0, IPL is not performed and starts immediately.

FIG. 1(b) shows a flowchart of a debug-only reset program. Six programs are stored in the ROM 12 with address B as the beginning. When the debug-only reset switch 7 of the processing device is pressed, the processing device hardware is reset and then linked to the debug-only reset program. This program only performs a self-check around the processor and starts immediately without checking the main memory.

[Effects of the Invention] According to the present invention, the restart time during debugging of a processing device with an automatic self-diagnosis function at startup can be shortened from about 20 seconds to 2 to 3 seconds, and debugging efficiency is significantly improved. can.

[Brief explanation of the drawing]

1(a) and 1(b) are flowcharts of an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a processing device system that is the background of the present invention, and FIG. 3 is an internal configuration of the processing device. 4 is a configuration diagram of a power-on flag and a power recovery control section, and FIG. 5 is a configuration diagram of a reset input reception section of a processor. DESCRIPTION OF SYMBOLS 1... Processing device, 2... Display device, 3... Input device, 4... Auxiliary storage device, 5- Operator panel. Agent Patent Attorney Akio Takahashi Fig. 1 (Kyu) F, UN No. 10 (b) LJN Fig. 2 (d) (b) No. 30 No. 5

Claims (1)

[Scope of Claims] 1. In a processing device comprising means for activating a reset from the outside, means for diagnosing the internal state by activating the reset and starting up if it is normal, and means for reporting it to the outside in the event of an abnormality, A plurality of reset activation means can be arbitrarily selected from among the above, and when the reset activation by the first reset activation means is received, all or part of the internal diagnosis is not performed, and the reset activation by the second reset activation means is performed. 1. A method for controlling start-up of a processing device, characterized in that all of the internal diagnoses are performed when receiving a process.