JPH03100737A - Fault diagnostic system - Google Patents

Abstract

PURPOSE:To analyze a fault without placing any load in a processor in an information processor by sending ou fault information to a diagnostic processor in parallel to recovery processing that the internal processor performs. CONSTITUTION:The processor 100 reads the contents of an error register 500 to detect error occurrence and if the error can be recovered, normal processing is carried on after its recovery. While the processor 100 begins to perform the recovery processing, the output of a gate 630 becomes '1' and the output of a gate 640 and the outputs of a register 650 and a gate 660 become '1' in order, to that the output ATT of a diagnostic processor becomes '1'. Then the diagnostic processor fetches the contents of the error register 500 through a multiplexer 700 in parallel to the recovery processing by the processor 100. Consequently, the diagnostic processor can obtain error information used to diagnose the fault of the information processor 1 without placing any load on the processor 100.

Description

TECHNICAL FIELD The present invention relates to a fault diagnosing method, and more particularly to a fault diagnosing method for a microprogram control type information processing apparatus.

BACKGROUND OF THE INVENTION An information processing system is an IR system that includes an information processing device that performs various types of processing, and a diagnostic device that diagnoses a failure in the information processing device or electric power. Conventionally, in such information processing systems, when a diagnostic processor in a diagnostic device diagnoses the information processing device, the following method has been adopted. The diagnostic processor periodically receives data indicating the status of the information processing device through an interface between the diagnostic processor and the information processing device (hereinafter referred to as the diagnostic bus), and transmits data to the information processing device according to the contents. restart, collect detailed information about the failure,
This is a method of starting up a diagnostic program within the information processing device.

Another method is to notify the diagnostic processor of the occurrence of an error through the diagnostic bus when a hardware failure occurs in the information processing device or when the processor detects an error. A method is conceivable in which a request is made to take over the information processing apparatus, and the diagnostic processor executes various operations on the information processing apparatus based on the received fault information. In this method, the diagnosis processor is often notified when a serious failure is detected within the information processing device.

As mentioned above, when a hardware failure is detected in an information processing device and a request is made to the diagnostic processor to receive the failure information, if the failure is serious, the processor in the information processing device will request the diagnostic processor if necessary. After performing the navel failure notification procedure, stop.

Furthermore, after that, recovery processing starts from the diagnostic processor, and restart processing from the diagnostic processor is executed.

On the other hand, if the failure detected in the information processing device can be recovered by the recovery process of the processor itself, the processor continues normal processing after executing the recovery process. In this case, the processor does not perform the notification procedure to the diagnostic processor. In this case, since information regarding a recoverable failure is not received by the diagnostic processor, there is a drawback that the failure cannot be analyzed.

In addition, executing the procedure to notify the diagnostic processor every time a recoverable failure occurs has the disadvantage that the processing procedure becomes complicated and the load on the processor increases, which has a large impact on the normal processing that continues. .

Purpose of the Invention The present invention has been made in order to solve the above-mentioned conventional drawbacks, and its purpose is to provide a fault diagnosis method for more effectively analyzing faults without placing a load on the processor in an information processing device. The goal is to provide the following.

Structure of the Invention The fault diagnosis method according to the present invention includes an information processing device including an internal processor that performs recovery processing for a fault within its own device, and a diagnostic processor that performs recovery processing for a fault that cannot be recovered by the internal processor. A fault diagnosis method for an information processing system having a diagnostic device including, when a fault occurs in the information processing device, fault information regarding the fault is sent to the diagnostic processor in parallel with recovery processing performed by the internal processor. It is characterized by the following.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system that employs a fault diagnosis method according to the present invention.

In the figure, the information processing system includes an information processing device 1,
The system includes a diagnostic device (not shown). It is assumed that the diagnostic device includes a diagnostic processor.

Further, the information processing device 1 includes a processor 100 and a ma.f.
A RAM 200 in which black instructions are stored, a data bus 300, an error register 500, an address register 610, a comparison register 820, and a notification register 65.
0, a multiplexer 700, and a counter 710.

The processor 100 stores the address of the microinstruction in RAM.
200, and extracts microinstructions from the RAM 200 and executes them, thereby controlling the entire information processing apparatus.

Data bus 300 is used by the processor;
Through this data bus 300, the processor 100 can read and write each register.

Various errors detected within the information processing device are signaled by error signal E.
These are held in each bit of the error register 500 as RRO to N, and some or all of these become a cause of an error trap. The contents of error register 500 can be read by processor 100 via data bus 800. Furthermore, the processor 10G can prohibit error trapping depending on the processing content to be executed.

That is, M A S which is the output of the processor 100
l(When the signal is '0', the AND gate 410 suppresses the output of the OR gate 420, which is the sum of errors, and the error trap signal 41 becomes 02. In this case, the processor 100 detects the error at an appropriate timing. register 500
reads the contents of the file and executes various error recovery processes depending on the contents.

The address register 61O holds the microinstruction address output by the processor 100 every cycle of the processor. In addition, this address register! The storage capacity 110 does not necessarily have to exist for all the pits of the microinstruction address.

In principle, the comparison register 620 stores the starting address of recovery processing for recoverable errors. In this example, the contents of the comparison register 62G are
The data is written from the processor 100 via the data bus 800 at startup. Also, in some cases, the hardware always has a fixed value in the comparison register 8.
It may be maintained at 2G, or may be set arbitrarily using a well-known DIP switch or the like.

Similar to the address register 810, the storage capacity of the comparison register 620 does not have to be equal to all the pits of the microinstruction address.

The gate 830 is actually made up of multiple EX-NOR circuits, and includes an address register 61O and a comparison register 620.
This is a circuit that compares the contents held with the two and outputs "1" if the contents match. That is, when the recovery process is started, its output becomes "1°."

Further, the output of this gate 630 becomes an input signal to one of the input terminals of the gate 640. Note that in this example, gate 6
30 is a coincidence detection circuit, but it may be a circuit that outputs "1" when a certain predetermined relationship, such as a magnitude relationship, between the address register 810 and the comparison register 620 is satisfied; It doesn't have to be a circuit.

The output of the gate 630 described above and the error trap signal when the error trap is enabled, that is, the NASK signal is "1", are input to the gate B40, and either one is "1".
If the angle is 1°, the output of the game 1-640 becomes 1°, which is input to a register 650 (hereinafter referred to as a notification register) that holds the cause of a notification signal to a diagnostic processor in a diagnostic device (not shown).

At least one input of notification register 650 is “
1'', a notification signal ATT to the exposure diagnostic processor becomes valid through gate 860, requesting the diagnostic processor to receive error information.

The reason why the data bus 800 is directly connected to the notification register 650 is that when the processor 100 detects a serious failure, the processor 100 registers “
This is because there may be a usage in which the CPU 10 writes "1", requests the diagnostic processor to retrieve data, then stops, and is restarted by the diagnostic processor.

The multiplexer 700 selects one of the contents of the error register 500 according to the select signal SEL and outputs it as a SIN signal, which is serial data, to the diagnostic processor. Note that the select signal SEL to the multiplexer 70G is the clock C on the diagnostic bus in the diagnostic device.
It is created in counter 710 in synchronization with LK.

Next, the operation of the information processing system having such a configuration will be explained.

When the SK signal is "1#" as the output of the processor 100, error trapping is enabled.Therefore, if an error occurs in this state, the output of the game) 41G becomes "1" and is trapped.The processor 100 is trapped and enters error trap processing, and at the same time, the output of gate 640 becomes "1#". Therefore, register 6
The outputs of 50 and 6o become "]#", and the output ATT to the diagnostic processor 100 becomes "1".

Then, the diagnostic processor executes error information collection processing and starts the clock on the diagnostic bus.

As a result, the diagnostic processor generates a select signal SEL in the counter 710 and receives the contents of the error register 500 which is serially outputted as a SIN signal through the multiplexer 7°U. During this time, the processor 100 executes recovery processing for the error in parallel with the operation of the diagnostic processor, and if recovery is possible, continues normal processing after the recovery processing.

Also, whether it is the output of the processor 100 or the MASK signal is '
When 0', error trapping is prohibited. In this case, the processor 100 reads the contents of the error register 500 at a suitable evening timing, detects the occurrence of an error, and if recovery is possible, resumes normal processing after recovery processing. here,
Since the comparison register 620 stores the start address of the recovery process in advance as described above, the processor 100
At the same time as starts the recovery process, the output of the gate 630 becomes '1'.Therefore, the output of the gate 640, the register 650, and the output of the gate 660 sequentially become '1', and the output ATT to the diagnostic processor becomes '1'. . Then, while the processor 100 executes the recovery process, the diagnostic processor takes in the contents of the error register 500 through the multiplexer 700.

In other words, according to the fault diagnosis method of the present invention, detailed information regarding the fault is received by the diagnostic processor while the processor is undergoing recovery processing, so that normal processing of the processor is not interrupted.

As described in detail, according to the fault diagnosis method of the present invention, a data collection request is notified to the diagnostic processor regardless of whether or not error trapping is prohibited, and the error content is determined to be recoverable. When an error occurs, the diagnostic processor can collect error information in parallel with the processor executing error recovery processing and subsequent normal processing, and can be used for failure analysis of information processing equipment, etc., without placing a load on the processor. This has the effect of being able to obtain error information.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of an information processing system that employs a fault diagnosis method according to the present invention. Description of symbols of main parts 100... Processor 200... RAM 500... Error register 81G... Address register 82G... Comparison register 650... Notification register 700... Multiplexer

Claims (1)

[Claims] (1) Information processing having an information processing device including an internal processor that performs recovery processing for a failure within its own device, and a diagnostic device including a diagnostic processor that performs recovery processing for a failure that cannot be recovered by the internal processor. A fault diagnosis method for a system, characterized in that when a fault occurs in the information processing device, fault information regarding the fault is sent to the diagnostic processor in parallel with recovery processing performed by the internal processor. Fault diagnosis method.