JPS6175931A - Central processor - Google Patents

Abstract

PURPOSE:To execute a program at a high speed by providing an internal memory part which stores the instructions or data in the addresses preceding the address which is under execution as well as the instructions or data on the addresses following the address under execution. CONSTITUTION:A controller 9 of a control part 2 pre-reads the instructions or data in the intervals of execution of instructions and stores them in an inter nal memory 3. The memory 3 stores N pieces of instructions or data up to an address PC-N which is ahead of an address PC of the instruction or data under execution by plural addresses together with M pieces of instructions or data up to an address PC+M which is behind the address PC by plural addresses. Therefore even an instruction for execution of the address preceding the address PC can be read out quickly from the memory 3 and executed.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a central processing 'tAf (central prO
Regarding c(!33!n(1 unit: Cr'U).

[Technical disadvantages of the invention and its problems] A central processing unit (hereinafter also referred to as CPU) reads out a program stored in an external memory and decodes this program with an instruction recorder to control each unit. The processor is configured to include a processor, an arithmetic unit that performs arithmetic operations on data to be transferred, and a look-ahead register that holds instructions and data up to N points beyond the address currently being executed.

By the way, depending on the contents of the instruction, there are instructions that are only internal to the CPU or instructions that take time, so by reading ahead the next instruction or data in advance and holding it in a register during the interval during instruction execution, program execution can be delayed. We are trying to speed up the process.

However, if the entire program is made up of sequential instructions, there will be no problem, but there are cases where programs include jump instructions or execute an address previous to the address currently being executed. As mentioned above, not only do the instructions or data read ahead and held in registers during the interval during instruction execution become meaningless, but also new instructions for execution must be fetched from the outside, which reduces the speed of the program. There is a problem that it cannot be implemented.

[Purpose of the Invention] The present invention has been made in view of the above circumstances, and is to achieve high-speed execution of a program even though there is an instruction to execute an address earlier than the address currently being executed. The purpose is to provide a central processing unit that can perform

[Summary of the Invention 1] A summary of the present invention for achieving the above object is that, in a central processing unit having a υ control unit that controls the operation of other units according to commands of a program, the control unit controls the current state of the program. It is characterized by having an internal memory section that stores instructions or data at addresses after the currently executed address, and also stores instructions or data at addresses before the currently executed address.

[Act of the Invention IMPAJ Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a central processing bag d, which is an embodiment of the present invention. A control unit 3 that controls the operation of the arithmetic unit and other units is controlled by the control unit 2, and stores instructions or data at addresses after the address where the program is currently being executed, and also stores instructions or data at addresses before the address where the program is currently being executed. This is an internal memory section that also stores instructions or data at addresses.

The control unit 2 includes an address register 4 that holds the address of an instruction to be executed, and an address buffer 5 that outputs the address held in the address register 4 to an external memory device (not shown) via an address bus. , a data register/buffer 76 for taking in the instruction at the address outputted via this address buffer 5 via the data bus, and this data register/buffer ? 6; an instruction recorder 8 for decoding the instructions held in the instruction register 7; 2 (c) Controller 9 that controls the operation of each unit connected outside and outside this CPU
It is composed of:

Next, the operation of the embodiment device having the above configuration will be explained.

Instructions and data are read from an external memory device (not shown) using the address held in the address register 4,
Instructions are input to the instruction register 7 via the data register/buffer 6, and data is input to the arithmetic unit 1 and held there. The instructions held in the instruction register 7 are read out by the instruction recorder 8 and are subjected to control by the controller.

On the other hand, the controller 9 performs pre-reading of commands or data at intervals during the execution of commands, and stores them in the internal memory section 3. For example, as shown in FIG.
), the addresses are multiple addresses before this address (PC), that is, addresses (PC-2), (PC-4), etc.
. N instructions or data up to (PC-N) are stored, and the addresses are a plurality of addresses after the address (PC), that is, addresses (PC+2) and (PC+4).

. . . M instructions or data up to (PC+M) are stored.

In this way, by prefetching the instruction or data, the internal memory unit 3 stores not only the instruction or data at the address after the address of the instruction or data currently being executed, but also the instruction or data at the previous address. Therefore, even if there is an instruction that executes an address that is higher than the address that is currently being executed, it can be quickly retrieved from the internal memory section 3 and executed, resulting in high-speed program execution. can be achieved.

Although one embodiment of the present invention has been described below, the present invention is not limited to the above embodiment, and it goes without saying that modifications can be made as appropriate within the scope of the gist of the present invention. .

[Effects of the Invention] As described above, according to the present invention, even if there is an instruction to execute an address earlier than the address currently being executed, the program can be executed at high speed. A processing device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of a central processing unit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example of storage in the internal memory section of the device shown in FIG. 1... Performance section, 2... ili control section, 3... Internal memory section.

Claims (1)

[Claims] In a central processing unit that has a control unit that controls the operations of other units according to instructions from a program, the control unit stores instructions or data at an address after the address where the program is currently being executed, and the instructions or data that are currently being executed. 1. A central processing unit comprising an internal memory unit that also stores instructions or data at an address before the current address.