JPS6175533A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6175533A JPS6175533A JP59196701A JP19670184A JPS6175533A JP S6175533 A JPS6175533 A JP S6175533A JP 59196701 A JP59196701 A JP 59196701A JP 19670184 A JP19670184 A JP 19670184A JP S6175533 A JPS6175533 A JP S6175533A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- electrode
- dummy
- substrate
- exploded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置に係り、特に、ブリップ・チップ
方式の半導体装置の冷却技術に適用して有効な技術に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a cooling technique for a blip-chip type semiconductor device.
フリップ・チップ方式の大規模集積回路等の半導体装置
は、多層配線になっている。このような半導体装置には
、半導体チップの放熱を良くするために、半田バンプ等
の放熱用ダミ突起電極を設けたものがある。Semiconductor devices such as flip-chip large-scale integrated circuits have multilayer wiring. Some of such semiconductor devices are provided with heat dissipating dummy protruding electrodes such as solder bumps in order to improve heat dissipation of the semiconductor chip.
本発明者は、 ＋？ｉｆ記の放熱用ダミ突起電極を有す
る半導体装置を検討した結果、前記放熱用ダミ突起電極
の接続部直下の多層配線中には多層の絶縁膜が形成され
ている。これらの多層配線は、熱伝導率が悪いため熱抵
抗が高くなり、半導体チップからの熱が突起電極に逃げ
にくいことを見い出した。The inventor is +? As a result of studying the semiconductor device having the dummy protruding electrode for heat dissipation as described in IF, a multilayer insulating film is formed in the multilayer wiring directly under the connection portion of the dummy protruding electrode for heat dissipation. It was discovered that these multilayer wirings have high thermal resistance due to poor thermal conductivity, making it difficult for heat from the semiconductor chip to escape to the protruding electrodes.
なお、フリップ・チップ方式による実装技術は、例えば
、サイエンスフォーラム社発行、超■、ＳＴデバイスハ
ンドブック、１９８３年１１月２８日発行、Ｐ２３５に
記載されている。Note that the mounting technology using the flip chip method is described in, for example, Science Forum Inc., Super ■, ST Device Handbook, November 28, 1983, p. 235.
本発明の目的は、フリップ・チップ方式の半導体装置に
おいて、半導体チップと基板との間の熱抵抗を低減する
ことができる技術を提供することにある。An object of the present invention is to provide a technique that can reduce thermal resistance between a semiconductor chip and a substrate in a flip-chip semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添４４図面によって明らかになるであ
ろう。The above and other objects and novel features of the present invention will become clear from the description of this specification and the attached 44 drawings.
本願において開示されろ発明のうち、代表的なものの概
要を説明すれは、下記のとおりである。Outline of typical inventions disclosed in this application is as follows.
すなわち、フリップ・チップ方式の半導体装置において
、半導体チップと基板との間に放熱用タミ突起電極を設
け、該放熱用ダミ突起電極と半導体チップとの接続部の
絶縁層を一層のみで構成したことにより、半導体チップ
と基板との間の熱抵抗を低減することかできるようにし
たものである。That is, in a flip-chip type semiconductor device, a heat dissipation stub electrode is provided between the semiconductor chip and the substrate, and the insulating layer at the connection portion between the heat dissipation stub electrode and the semiconductor chip is composed of only one layer. This makes it possible to reduce the thermal resistance between the semiconductor chip and the substrate.
以下、本発明の構成について、実施例とともに説明する
。Hereinafter, the configuration of the present invention will be explained along with examples.
なお、全回において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第１図及び第２図は、本発明をマルチチップ型半導体装
置に適用した実施例Ｉの構成を説明するための図であり
、第１図は、そのリードを省略した全体構成の断面図、
第２図は、第１図のＯ印Ａで囲んだ部分の拡大断面図で
ある。1 and 2 are diagrams for explaining the configuration of Embodiment I in which the present invention is applied to a multi-chip semiconductor device, and FIG. 1 is a sectional view of the entire configuration with the leads omitted;
FIG. 2 is an enlarged sectional view of the portion surrounded by O mark A in FIG. 1.
第１図及び第２図において、１はシリコン等の半導体か
らなる基板であり、多層配線部２が設けられでいる。３
けシリコン等の半導体からなる半導体チップであり、多
層配線か設けられている。In FIGS. 1 and 2, reference numeral 1 denotes a substrate made of a semiconductor such as silicon, on which a multilayer wiring section 2 is provided. 3
It is a semiconductor chip made of a semiconductor such as silicon, and is provided with multilayer wiring.
この半導体チップ３は半Ｉ１１バンプ等の突起電極４に
より基板ｌと電気的に接続されている。５は半導体チッ
プ３と一層の絶縁膜で絶縁された放熱用ダミ突起電極で
あり、半導体チップ３で発生された熱を基板ｌ側に伝達
するためのものである。この放熱用ダミ突起電極５と゛
１′：導体チップ３との接続部は、第２図に示すように
、半導体チップ３の下にアルミナ（Ａ Ｑ ２０３）等
の第１絶縁膜６が設けられ、その下にアルミニウム等か
らなる第１乃至第３配［７，８，９，突起電極形成用下
地金属１！ｉｉ １０及び放熱用タミ突起電極５か順次
設けられている。１１．１２及び１３は第２乃至第４絶
縁膜である。This semiconductor chip 3 is electrically connected to the substrate 1 by a protruding electrode 4 such as a half I11 bump. Reference numeral 5 designates a heat dissipating dummy protruding electrode insulated from the semiconductor chip 3 by a single layer of insulating film, and is used to transmit heat generated in the semiconductor chip 3 to the substrate l side. As shown in FIG. 2, a first insulating film 6 made of alumina (AQ 203) or the like is provided under the semiconductor chip 3 to connect the heat dissipating dummy protruding electrode 5 and the conductor chip 3. As shown in FIG. , and below the first to third electrodes made of aluminum or the like [7, 8, 9, base metal for forming protruding electrodes 1! ii 10 and a heat dissipation tang protrusion electrode 5 are provided in this order. 11, 12 and 13 are second to fourth insulating films.
前記突起電極形成川下地金属膜１０は、Ｃｒ／Ｃｒ ＋
Ｃ”、 ｌ］／Ｃｕ／Ａ １１からなる多層金属膜で構
成されている。The underlying metal film 10 on which the protruding electrodes are formed is Cr/Cr +
It is composed of a multilayer metal film consisting of C'', l]/Cu/A11.
前記のことかられかるように、本実施例Ｉによれば、半
導体チップ３と突起電極４との間に一つの絶縁膜６しか
介在していないので、半導体チップ３と突起電極４との
間の熱抵抗を低減することができる。As can be seen from the above, according to the present embodiment I, since only one insulating film 6 is interposed between the semiconductor chip 3 and the protruding electrodes 4, the gap between the semiconductor chip 3 and the protruding electrodes 4 is can reduce the thermal resistance of
第３図は、本発明の他の実施例の半導体チップと放熱用
ダミ突起電極との接続部の構成を示す図である。FIG. 3 is a diagram showing the configuration of a connecting portion between a semiconductor chip and a heat dissipating dummy protrusion electrode according to another embodiment of the present invention.
本実施例Ｈの半導体装置の半導体チップ３と放熱用ダミ
突起電極５との接続部は、第３図に示すように、半導体
チップ３の直ぐ下に第１配線７が設けられ、第２層目に
第１絶縁膜６が設けられたものであり、それ以下は実施
例Ｉと同じ構成となっている。このように、半導体チッ
プ３と放熱用ダミ突起電極５との間に絶縁する絶縁膜が
一つ介在していれば、何層口に絶縁膜を設けても、前記
実施例Ｉと同等に熱抵抗を低減することができる。As shown in FIG. 3, the connection portion between the semiconductor chip 3 and the heat dissipating dummy protrusion electrode 5 of the semiconductor device of Example H is such that the first wiring 7 is provided immediately below the semiconductor chip 3, and the second layer The first insulating film 6 is provided in the first insulating film, and the rest has the same structure as in Example I. In this way, if one insulating film is interposed between the semiconductor chip 3 and the heat dissipating dummy protruding electrode 5, no matter how many layers the insulating film is provided, the heat can be maintained at the same level as in Embodiment I. Resistance can be reduced.
以上説明したように、本願で開示した新規な技術によれ
ば、次に述べるような効果を得ることができる。As explained above, according to the new technology disclosed in this application, the following effects can be obtained.
（１）フリップ・チップ方式の半導体装置において、半
導体チップと基板との間に放熱用ダミ突起電極を設け、
該放熱用ダミ突起電極と半導体チップとの接続部の絶縁
を一層のみで構成したことにより、半導体チップと基板
との間の熱抵抗を低減することができる。(1) In a flip-chip type semiconductor device, a dummy protruding electrode for heat dissipation is provided between the semiconductor chip and the substrate,
By configuring the insulation of the connecting portion between the heat dissipating dummy protruding electrode and the semiconductor chip using only one layer, it is possible to reduce the thermal resistance between the semiconductor chip and the substrate.
（２）前記（１）により、半導体チップの放熱効率を向
上させることができるので、半導体装置の長寿命化がは
かれる。(2) According to (1) above, the heat dissipation efficiency of the semiconductor chip can be improved, so that the life of the semiconductor device can be extended.
（３）前記（１）により、半導体チップの放熱効率を向
−１−させることができるので、半導体装置の信頼性を
向−トさせることができる。(3) According to (1) above, the heat dissipation efficiency of the semiconductor chip can be improved by 1-1, so the reliability of the semiconductor device can be improved.
以−１−１本発明を実施例にもとすき具体的に説明した
が、本発明は、前記実施例に限定されるものではなく、
その要旨を逸脱しない範囲において種々変更可能である
ことはいうまでもない。Below-1-1 The present invention has been specifically explained using Examples, but the present invention is not limited to the Examples.
It goes without saying that various changes can be made without departing from the gist of the invention.
例えば、前記実施例では、基板を半導体基板としたが、
ベリリアを少量含有した炭化シリコン（Ｓ ｉ Ｃ）基
板又はセラミック基板等の絶縁基板にしてもよいことは
勿論である。For example, in the above embodiment, the substrate is a semiconductor substrate, but
Of course, an insulating substrate such as a silicon carbide (S i C) substrate or a ceramic substrate containing a small amount of beryllia may be used.
第１図及び第２図は、本発明をマルチチップ型半導体装
置に適用した実施例Ｉの構成を説明するための図であり
、
第１図は、そのリードを省略した全体構成の断面図、
第２図は、第１図の０印Ａで囲んだ部分の拡大断面図、
第３図は、本発明の他の実施例の半導体チップと放熱用
ダミ突起電極との接続部の構成を示す図である。
図中、ｌ □ＩＥ、板、２・多層配線、３・・・１１＋
、導体チップ、４・・突起電極、５・・放熱用ダミ突起
電極、６・・・第１絶縁膜、７．８．９・・第１乃至第
３配線、ｌＯ・・・突起電極形成用下地金属膜、１１，
１２゜１３・・第２乃至第４絶縁膜である。
第 １ 図
第 ３ 図1 and 2 are diagrams for explaining the configuration of Embodiment I in which the present invention is applied to a multi-chip semiconductor device. FIG. 1 is a cross-sectional view of the overall configuration with the leads omitted; FIG. 2 is an enlarged cross-sectional view of the part surrounded by the 0 mark A in FIG. 1, and FIG. 3 shows the configuration of the connection part between the semiconductor chip and the heat dissipation dummy protrusion electrode in another embodiment of the present invention. It is a diagram. In the diagram, l □IE, board, 2/multilayer wiring, 3...11+
, conductor chip, 4... protruding electrode, 5... dummy protruding electrode for heat dissipation, 6... first insulating film, 7.8.9... first to third wiring, lO... for forming protruding electrode Base metal film, 11,
12°13: Second to fourth insulating films. Figure 1 Figure 3
Claims (1)
チップと基板との間に放熱用ダミ突起電極を設け、該放
熱用ダミ突起電極と半導体チップとの接続部の絶縁層を
一層のみで構成したことを特徴とする半導体装置。A flip-chip type semiconductor device, characterized in that a heat dissipation dummy protrusion electrode is provided between the semiconductor chip and the substrate, and the insulating layer at the connection portion between the heat dissipation dummy protrusion electrode and the semiconductor chip is composed of only one layer. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59196701A JPS6175533A (en) | 1984-09-21 | 1984-09-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59196701A JPS6175533A (en) | 1984-09-21 | 1984-09-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6175533A true JPS6175533A (en) | 1986-04-17 |
Family
ID=16362145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59196701A Pending JPS6175533A (en) | 1984-09-21 | 1984-09-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6175533A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6829149B1 (en) * | 1997-08-18 | 2004-12-07 | International Business Machines Corporation | Placement of sacrificial solder balls underneath the PBGA substrate |
-
1984
- 1984-09-21 JP JP59196701A patent/JPS6175533A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6829149B1 (en) * | 1997-08-18 | 2004-12-07 | International Business Machines Corporation | Placement of sacrificial solder balls underneath the PBGA substrate |
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