JPH04116960A - Semiconductor circuit device - Google Patents
Semiconductor circuit deviceInfo
- Publication number
- JPH04116960A JPH04116960A JP2237926A JP23792690A JPH04116960A JP H04116960 A JPH04116960 A JP H04116960A JP 2237926 A JP2237926 A JP 2237926A JP 23792690 A JP23792690 A JP 23792690A JP H04116960 A JPH04116960 A JP H04116960A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- copper
- glass
- circuit board
- composite material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 239000010949 copper Substances 0.000 claims abstract description 17
- 239000011521 glass Substances 0.000 claims abstract description 13
- 239000002131 composite material Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- 230000008646 thermal stress Effects 0.000 abstract description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 7
- 239000011733 molybdenum Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 235000011837 pasties Nutrition 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 239000000843 powder Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000004898 kneading Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁回路基板上に半導体素子を実装する、例え
ば混成集積回路装置等の半導体回路装置において、半導
体素子の下側に備えるヒートシンクに関するものである
。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a heat sink provided under a semiconductor element in a semiconductor circuit device such as a hybrid integrated circuit device in which a semiconductor element is mounted on an insulated circuit board. It is.
第２図に従来の半導体回路装置としての混成集積回路装
置の断面構造図を示す。FIG. 2 shows a cross-sectional structural diagram of a hybrid integrated circuit device as a conventional semiconductor circuit device.
図中７はアルミニウム製の２次ヒートシンクであり、２
次ヒートシンク７上にはシリコン樹脂接着層６により絶
縁回路基板５が接合されており、絶縁回路基板５の上に
はモリブデン又は銅製の１次ヒートシンク３及び半導体
素子としてのパワートランジスタチップ１が順次はんだ
付されている。In the figure, 7 is a secondary heat sink made of aluminum.
An insulated circuit board 5 is bonded onto the heat sink 7 by a silicone resin adhesive layer 6, and a primary heat sink 3 made of molybdenum or copper and a power transistor chip 1 as a semiconductor element are sequentially soldered onto the insulated circuit board 5. It is attached.
図中２及び４ははんだ層である。パワートランジスタチ
ップ１と絶縁回路基板５の導体部とはアルミニウム製の
ワイヤ８により結線されている。In the figure, 2 and 4 are solder layers. The power transistor chip 1 and the conductor portion of the insulated circuit board 5 are connected by a wire 8 made of aluminum.
以上の如く構成された混成集積回路装置では、パワート
ランジスタチップ１を作動させた時に発生する熱は、１
次ヒートシンク３及び絶縁回路基板５を経由し、２次ヒ
ートシンク７に放散される。In the hybrid integrated circuit device configured as described above, the heat generated when the power transistor chip 1 is operated is 1
It is radiated to the secondary heat sink 7 via the secondary heat sink 3 and the insulated circuit board 5.
パワートランジスタチップｌの上側にはシリコンゲルが
充填されているが、シリコンゲルに放熱される量は少な
く、パワートランジス・タチップ１の上側への放熱は主
としてワイヤ８による。Although the upper side of the power transistor chip 1 is filled with silicon gel, the amount of heat radiated to the silicon gel is small, and the heat radiated to the upper side of the power transistor chip 1 is mainly by the wire 8.
パワートランジスタチップ１が作動する時に発生する熱
はパワートランジスタチップ１の下方に放散され、この
ときパワートランジスタチップｌと１次ヒートシンク３
との間及び１次ヒートシンク３と絶縁回路基板５との間
に温度差が生じ、熱応力が発生する。１次ヒートシンク
３の材料としては、パワートランジスタチップ１と１次
ヒートシンク３との間及び１次ヒートシンク３と絶縁回
路基板５との間の線膨張率の差を小さくしてはんだ層２
及びはんだ層４に加わる熱応力を低減させ、亀裂の発生
率を低減させるために、現在はモリブデンがよく使用さ
れている。Heat generated when the power transistor chip 1 operates is dissipated below the power transistor chip 1, and at this time, the power transistor chip 1 and the primary heat sink 3
A temperature difference occurs between the primary heat sink 3 and the insulated circuit board 5, and thermal stress occurs. The material for the primary heat sink 3 is a solder layer 2 that reduces the difference in linear expansion coefficient between the power transistor chip 1 and the primary heat sink 3 and between the primary heat sink 3 and the insulated circuit board 5.
Molybdenum is currently often used to reduce the thermal stress applied to the solder layer 4 and reduce the incidence of cracks.
モリブデンと銅とを比較するとモリブデンの熱伝導率は
１．４Ｗ／ｃ１１／ ”Ｃへｅｃであり、銅の熱伝導率
４．０１１／ｃ＠／ ｔ’ ／ｓｅｃより小さく、放熱
性が悪い。従って１次ヒートシンク３の材料としてモリ
ブデンを使用した場合には銅を使用した場合と比較して
パワートランジスタチップ１の表面温度が上昇するので
、パワートランジスタチップ１よりワイヤ８を通じて放
熱される量が増加し、ワイヤ８の端面に生じる熱応力も
増加する。そして端面が熱疲労し、ワイヤ８が剥離する
等の問題があった。Comparing molybdenum and copper, the thermal conductivity of molybdenum is 1.4 W/c11/'C to ec, which is lower than the thermal conductivity of copper, 4.011/c@/t'/sec, and has poor heat dissipation. Therefore, when molybdenum is used as the material for the primary heat sink 3, the surface temperature of the power transistor chip 1 increases compared to when copper is used, so the amount of heat dissipated from the power transistor chip 1 through the wire 8 increases. However, the thermal stress generated on the end face of the wire 8 also increases.Therefore, there are problems such as thermal fatigue of the end face and peeling of the wire 8.
本発明は斯かる事情に鑑みてなされたものであり、１次
ヒートシンクを銅とガラスとの複合材料から構成するこ
とにより線膨張率を小さくし、はんだ層に作用する熱応
力を低減させてその亀裂の発生を防止し、また熱伝導率
を高くして例えばパワートランジスタチップ等の半導体
素子の温度上昇を抑制し、半導体素子と基板の導体部と
を接続するワイヤに伝達される熱量を減少させてワイヤ
の劣化及び剥離を防止した例えば混成集積回路装置等の
半導体回路装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and consists of a primary heat sink made of a composite material of copper and glass, thereby reducing the linear expansion coefficient and reducing the thermal stress acting on the solder layer. It prevents the occurrence of cracks, increases thermal conductivity, suppresses the temperature rise of semiconductor elements such as power transistor chips, and reduces the amount of heat transferred to the wires that connect the semiconductor element and the conductor part of the substrate. An object of the present invention is to provide a semiconductor circuit device, such as a hybrid integrated circuit device, in which deterioration and peeling of wires are prevented.
本発明に係る半導体回路装置は、半導体素子の下側に設
けるヒートシンクの材料を銅とガラスとの複合材料にし
たものである。前記複合材料は、銅粉末とガラスとを混
練してペースト状にし、体焼結することにより得られる
。In the semiconductor circuit device according to the present invention, the heat sink provided below the semiconductor element is made of a composite material of copper and glass. The composite material is obtained by kneading copper powder and glass to form a paste and sintering the paste.
本発明においては、ヒートシンクは銅とガラスとの複合
材料からなり、銅製のヒートシンクと同程度に熱伝導率
が高く、しかも線膨張率が小さいので熱応力の発生を抑
制し、半導体素子の温度上昇を抑制する。In the present invention, the heat sink is made of a composite material of copper and glass, and has high thermal conductivity comparable to that of a copper heat sink, and has a small coefficient of linear expansion, so it suppresses the generation of thermal stress and increases the temperature of semiconductor elements. suppress.
以下、本発明をその実施例を示す図面に基づいて具体的
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.
第１図に本発明の半導体回路装置としての混成集積回路
装置の断面構造図を示す。FIG. 1 shows a cross-sectional structural diagram of a hybrid integrated circuit device as a semiconductor circuit device of the present invention.
図中７はアルミニウム製の２次ヒートシンクであり、２
次ヒートシンク７上にはシリコン樹脂接着層６により絶
縁回路基板５が接合されており、絶縁回路基板５の上に
はモリブデン製のｌヒートシンク９及び半導体素子とし
てのパワートランジスタチップ１が順次はんだ付されて
いる。図中２及び４ははんだ層である。In the figure, 7 is a secondary heat sink made of aluminum.
Next, an insulated circuit board 5 is bonded onto the heat sink 7 by a silicone resin adhesive layer 6, and a heat sink 9 made of molybdenum and a power transistor chip 1 as a semiconductor element are sequentially soldered onto the insulated circuit board 5. ing. In the figure, 2 and 4 are solder layers.
パワートランジスタチップ１と絶縁回路基板の導体部５
とはアルミニウム製のワイヤ８により結線されている。Power transistor chip 1 and conductor portion 5 of insulated circuit board
and are connected by an aluminum wire 8.
本発明では、１次ヒートシンク９の材料として銅とガラ
スとの複合材料を使用している。この複合材料は銅の含
有量が９０重量％になるように銅粉末とガラスとを混練
してペースト状にし、金型に流し込んで８００℃で一体
焼結することにより得られる。In the present invention, a composite material of copper and glass is used as the material for the primary heat sink 9. This composite material is obtained by kneading copper powder and glass to form a paste so that the copper content is 90% by weight, pouring it into a mold, and integrally sintering it at 800°C.
以上の如く構成された混成集積回路装置では、パワート
ランジスタチップ１を作動させた時に発生する熱は、１
次ヒートシンク９の熱伝導率が３．６Ｗ／ｃｍ／ ’Ｃ
／ｓｅｃであり、銅と同程度に高いので、これにより効
果的に放散される。従ってパワートランジスタチップ１
の温度上昇が抑制され、ワイヤ８を通じて放熱される量
が減少し、ワイヤ８の端面の熱疲労が減少する。In the hybrid integrated circuit device configured as described above, the heat generated when the power transistor chip 1 is operated is 1
NextThe thermal conductivity of heat sink 9 is 3.6W/cm/'C
/sec, which is as high as copper, so it is effectively dissipated. Therefore, power transistor chip 1
temperature rise is suppressed, the amount of heat radiated through the wire 8 is reduced, and thermal fatigue of the end face of the wire 8 is reduced.
そして、１次ヒートシンク９はガラス成分を含有するの
で線膨張率はその分小さくなり、パワートランジスタチ
ップ１と１次ヒートシンク９との間及び１次ヒートシン
ク９と絶縁回路基板５との間の線膨張率の差が小さく、
はんだ層２及びはんだ層４に加わる熱応力が小さいので
これらに亀裂が生じることがない。Since the primary heat sink 9 contains a glass component, the coefficient of linear expansion is reduced accordingly, and the linear expansion between the power transistor chip 1 and the primary heat sink 9 and between the primary heat sink 9 and the insulated circuit board 5 is reduced accordingly. The difference in rates is small;
Since the thermal stress applied to the solder layer 2 and the solder layer 4 is small, cracks do not occur in them.
なお、１次ヒートシンク９の銅の含有率は略８０重量％
にしてもよい。Note that the copper content of the primary heat sink 9 is approximately 80% by weight.
You can also do this.
そして本発明の実施例では、半導体素子としてパワート
ランジスタを適用した場合につきて説明しているが、何
らこれに限定されるものではなく、他のトランジスタ及
びシリコン制御整流素子等信の半導体素子を適用するこ
とが可能である。In the embodiments of the present invention, a case is explained in which a power transistor is applied as a semiconductor element, but the present invention is not limited to this in any way, and other semiconductor elements such as a transistor and a silicon-controlled rectifier element can be applied. It is possible to do so.
さらに実施例では混成集積回路装置として構成した場合
につき説明しているが、何らこれに限定されるものでは
なく、他の半導体回路装置にも適用できるのは言うまで
もない。Furthermore, although the embodiments have been described with reference to a case where the present invention is configured as a hybrid integrated circuit device, it goes without saying that the present invention is not limited to this and can be applied to other semiconductor circuit devices.
以上の如く本発明の半導体回路装置においては、１次ヒ
ートシンクを銅とガラスとの複合材料から構成している
ので、半導体素子と１次ヒートシンクとの間及び１次ヒ
ートシンクと絶縁回路基板との間の線膨張率の差が小さ
くなり、これらの部材を接合しているはんだ層に作用す
る熱応力が減少し、その亀裂の発生が防止される。また
、熱伝導率が高いので、半導体素子の温度上昇が抑制さ
れ、半導体素子と基板の導体部とを接続するワイヤに伝
達される熱量が減少してワイヤの劣化及び剥離が防止さ
れる等、本発明は優れた効果を奏するものである。As described above, in the semiconductor circuit device of the present invention, since the primary heat sink is made of a composite material of copper and glass, there are gaps between the semiconductor element and the primary heat sink and between the primary heat sink and the insulated circuit board. The difference in the linear expansion coefficients of these members is reduced, the thermal stress acting on the solder layer that joins these members is reduced, and the generation of cracks is prevented. In addition, since the thermal conductivity is high, the temperature rise of the semiconductor element is suppressed, and the amount of heat transferred to the wire connecting the semiconductor element and the conductor part of the substrate is reduced, preventing deterioration and peeling of the wire, etc. The present invention has excellent effects.
第１図は本発明に係る混成集積回路装置の断面構造図、
第２図は従来の混成集積回路装置の断面構造図である。
１・・・パワートランジスタチップ ２．４・・・はん
だＭ ５・・・絶縁回路基板 ６・・・シリコン樹脂接
着層 ７・・・２次ヒートシンク ８・・・ワイヤ ９
・・・１次ヒートシンク
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄
第
］
図
第
図FIG. 1 is a cross-sectional structural diagram of a hybrid integrated circuit device according to the present invention;
FIG. 2 is a cross-sectional structural diagram of a conventional hybrid integrated circuit device. 1... Power transistor chip 2.4... Solder M 5... Insulated circuit board 6... Silicon resin adhesive layer 7... Secondary heat sink 8... Wire 9
...Primary heat sink In the figures, the same reference numerals indicate the same or corresponding parts. Agent: Yudai Oiwa]
Claims (1)
子を実装した半導体回路装置において、前記ヒートシン
クの材料が銅とガラスとの 複合材料であることを特徴とする半導体回路装置。(1) A semiconductor circuit device in which a semiconductor element is mounted on an insulated circuit board via a heat sink, wherein the material of the heat sink is a composite material of copper and glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237926A JPH04116960A (en) | 1990-09-07 | 1990-09-07 | Semiconductor circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237926A JPH04116960A (en) | 1990-09-07 | 1990-09-07 | Semiconductor circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04116960A true JPH04116960A (en) | 1992-04-17 |
Family
ID=17022506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2237926A Pending JPH04116960A (en) | 1990-09-07 | 1990-09-07 | Semiconductor circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04116960A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545598A (en) * | 1993-02-12 | 1996-08-13 | Ngk Spark Plug Co., Ltd. | High heat conductive body and wiring base substrate fitted with the same |
| US20120134154A1 (en) * | 2000-10-16 | 2012-05-31 | Osram Ag | Configuration of Multiple LED Module |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412404A (en) * | 1987-07-06 | 1989-01-17 | Hitachi Ltd | Conductor material |
-
1990
- 1990-09-07 JP JP2237926A patent/JPH04116960A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412404A (en) * | 1987-07-06 | 1989-01-17 | Hitachi Ltd | Conductor material |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545598A (en) * | 1993-02-12 | 1996-08-13 | Ngk Spark Plug Co., Ltd. | High heat conductive body and wiring base substrate fitted with the same |
| US20120134154A1 (en) * | 2000-10-16 | 2012-05-31 | Osram Ag | Configuration of Multiple LED Module |
| US8511855B2 (en) * | 2000-10-16 | 2013-08-20 | Osram Gmbh | Configuration of multiple LED module |
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