JP2005285885A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005285885A
JP2005285885A JP2004094135A JP2004094135A JP2005285885A JP 2005285885 A JP2005285885 A JP 2005285885A JP 2004094135 A JP2004094135 A JP 2004094135A JP 2004094135 A JP2004094135 A JP 2004094135A JP 2005285885 A JP2005285885 A JP 2005285885A
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ceramic substrate
semiconductor device
heat sink
main surface
substrate
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Takayuki Naba
隆之 那波
Atsushi Kajiwara
淳志 梶原
Min Tai Kao
カオ・ミン・タイ
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Toshiba Corp
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Toshiba Corp
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device equipped with an insulating circuit substrate comprising a ceramic board to which a metal board is bonded, which withstands repeated tests to provide excellent reliability, and reduced thermal resistance from a chip to a heatsink. <P>SOLUTION: In the power semiconductor device equipped with an insulating circuit board comprising a ceramic board 3 and a heatsink 2 which are bonded together, the ceramic board and heatsink are directly bonded. This enables the semiconductor device to withstand repeated tests (thermal cycle tests) and obtain excellent reliability, and to simultaneously reduce a thermal resistance (transient thermal resistance) from a chip to a heatsink, thus stabilizing chip characteristics as well as preventing a thermal failure to obtain reliability. When the ceramic substrate and heatsink metal, such as Cu or the like, are bonded by an alloy including resin, it is possible to reduce the warpage of the substrate after bonding which is caused by a difference in coefficient of linear expansion between ceramic and metal, thereby enabling the reduction of a stress occurring on the chip or ceramic substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の構造に係り、とくにＴＣＴやＴＦＴなどの繰り返し試験に対する信頼性と、半導体チップからヒートシンクにかけての低熱抵抗を有するパワー半導体装置に関するものである。   The present invention relates to a structure of a semiconductor device, and more particularly to a power semiconductor device having reliability for repeated tests such as TCT and TFT and low thermal resistance from a semiconductor chip to a heat sink.

従来、ＩＧＢＴモジュールなどパワー半導体装置の絶縁回路部デザインは、セラミックス基板の一方の面（第１の主面）に回路パターン銅板（以下、表Ｃｕという）と他方の面（第２の主面）に放熱用銅板（以下、裏Ｃｕという）とが接合されたＤＢＣ（Direct Bonding Cu ）基板等が用いられ、この表Ｃｕ上に半導体チップを高温はんだによってはんだ付けした後、裏ＣｕとＣｕヒートシンク（Ｃｕベース）とを６３Ｓｎ−Ｐｂ共晶はんだによりリフローはんだ付けした構造となっている。   Conventionally, an insulating circuit portion design of a power semiconductor device such as an IGBT module has a circuit pattern copper plate (hereinafter referred to as a table Cu) on one surface (first main surface) of a ceramic substrate and the other surface (second main surface). A DBC (Direct Bonding Cu) substrate or the like bonded to a heat dissipation copper plate (hereinafter referred to as back Cu) is used. After soldering a semiconductor chip on this front Cu with high-temperature solder, the back Cu and Cu heat sink ( Cu base) is reflow soldered with 63Sn—Pb eutectic solder.

図５は、従来のＩＧＢＴモジュールの断面図である。ＩＧＢＴが作り込まれたシリコンチップ１０１は、セラミックス基板１０３の第１の主面に形成された表Ｃｕ１０４上にマウントはんだ１０７によって接合されている。そして、セラミックス基板１０３は、第２の主面に裏Ｃｕ１０５が形成されている。セラミックス基板１０３は、この裏Ｃｕ１０５を介してリフローはんだ１０８によってＣｕヒートシンク１０２に接合されている。シリコンチップ１０１と表Ｃｕ１０４とは、Ａｌなどからなるボンディングワイヤ１０６によって電気的に接続されている。   FIG. 5 is a cross-sectional view of a conventional IGBT module. The silicon chip 101 in which the IGBT is built is joined by a mount solder 107 on the front Cu 104 formed on the first main surface of the ceramic substrate 103. The ceramic substrate 103 has a back Cu 105 formed on the second main surface. The ceramic substrate 103 is joined to the Cu heat sink 102 by reflow solder 108 through the back Cu 105. The silicon chip 101 and the surface Cu 104 are electrically connected by a bonding wire 106 made of Al or the like.

この裏Ｃｕが存在することにより、接合プロセスが多くなること及び裏Ｃｕ自体の熱抵抗のためパッケージとしての熱抵抗の低減が阻害されていた。さらに裏ＣｕとＣｕヒートシンクとのはんだ接合強度よりセラミックス基板と裏Ｃｕとの接合強度の方が大きいために、ＴＣＴによる応力によってはんだクラックが発生し脆化し易く、とくにＥＶ用など車載関係に使用されるパッケージでは耐脆化性の向上が求められていた。ＩＧＢＴモジュールの従来技術は、例えば、特許文献１に記載されている。   The presence of the back Cu hinders the reduction of the thermal resistance as a package due to the increased bonding process and the thermal resistance of the back Cu itself. Furthermore, since the bonding strength between the ceramic substrate and the back Cu is greater than the solder bonding strength between the back Cu and Cu heat sink, solder cracks are likely to occur due to the stress caused by TCT, and are especially used for automotive applications such as for EVs. In such packages, improvement in brittleness resistance has been demanded. The prior art of the IGBT module is described in Patent Document 1, for example.

この裏Ｃｕが存在することにより、接合プロセスが多くなること及び裏Ｃｕ自体の熱抵抗のためパッケージとしての熱抵抗の低減が阻害されていた。さらに裏ＣｕとＣｕヒートシンクとのはんだ接合強度よりセラミックス基板と裏Ｃｕとの接合強度の方が大きいために、ＴＣＴによる応力によってはんだクラックが発生し脆化し易く、とくにＥＶ用など車載関係に使用されるパッケージでは耐脆化性の向上が求められていた。   The presence of the back Cu hinders the reduction of the thermal resistance as a package due to the increased bonding process and the thermal resistance of the back Cu itself. Furthermore, since the bonding strength between the ceramic substrate and the back Cu is greater than the solder bonding strength between the back Cu and Cu heat sink, solder cracks are likely to occur due to the stress caused by TCT, and are especially used for automotive applications such as for EVs. In such packages, improvement in brittleness resistance has been demanded.

もし仮に裏Ｃｕをなくして直接ヒートシンクをセラミックス基板に接合したとすると、線膨張係数差により非常に大きな反りが発生し、セラミックス基板に強度の小さい窒化アルミニウム（ＡｌＮ）基板を使用した場合では接合後に基板が割れたり、あるいは強度の大きい窒化ケイ素（ＳｉＮ）基板等を使用した場合でも接合後には割れなくてもＴＣＴの比較的低サイクルで割れることが判明しているのでこの様な構造のものは実用化されていなかった。
特開平８−１６７７１６号公報 If the heat sink is directly bonded to the ceramic substrate without the back Cu, a very large warpage occurs due to the difference in linear expansion coefficient. Even if the substrate is cracked or a high-strength silicon nitride (SiN) substrate is used, it has been found that it does not crack after bonding, but it breaks at a relatively low cycle of TCT. It was not put into practical use.
JP-A-8-167716

本発明は、このような事情によりなされたものであり、セラミックス基板に金属板を接合した絶縁回路基板を搭載するＩＧＢＴモジュールなどの半導体装置において、熱サイクル試験などの繰り返し試験の信頼性に優れ、同時にチップからヒートシンクにかけての熱抵抗の低減された半導体装置を提供することを目的としている。   The present invention has been made under such circumstances, and in a semiconductor device such as an IGBT module mounted with an insulating circuit board in which a metal plate is bonded to a ceramic substrate, it is excellent in reliability of repeated tests such as a thermal cycle test, At the same time, an object of the present invention is to provide a semiconductor device with reduced thermal resistance from the chip to the heat sink.

上記目的を達成するために、本発明の半導体装置の一態様は、半導体チップと、前記半導体チップが第１の主面上に搭載されたセラミックス基板と、前記半導体チップが接合されている前記第１の主面に形成された回路パターンと、前記セラミックス基板の第１の主面とは反対側の第２の主面に直接接しているヒートシンクとを備えていることを特徴としている。
また、本発明の半導体装置は、半導体チップと、前記半導体チップが第１の主面上に搭載されたセラミックス基板と、前記半導体チップが接合された第１の主面に形成された回路パターンと、前記セラミックス基板の第１の主面とは反対側の第２の主面に接着剤を介して接しているヒートシンクとを備えていることを特徴としている。 In order to achieve the above object, according to one aspect of the semiconductor device of the present invention, a semiconductor chip, a ceramic substrate on which the semiconductor chip is mounted on a first main surface, and the semiconductor chip are joined. 1 is provided with a circuit pattern formed on one main surface and a heat sink directly in contact with a second main surface opposite to the first main surface of the ceramic substrate.
The semiconductor device of the present invention includes a semiconductor chip, a ceramic substrate on which the semiconductor chip is mounted on a first main surface, and a circuit pattern formed on the first main surface to which the semiconductor chip is bonded. And a heat sink that is in contact with the second main surface opposite to the first main surface of the ceramic substrate via an adhesive.

本発明によれば、主としてヒートシンクとセラミックス間に従来から存在していた放熱用金属をなくすことによって、熱抵抗の低減が達成される。また、セラミックス基板とＣｕ等のヒートシンク金属とを樹脂を含むはんだ合金で接合する場合は、従来より問題となっていたセラミックスと金属との線膨張係数差に起因する接合後の基板反りを低減でき、その結果、チップ、基板に発生する応力低減が図られ、熱サイクル試験によるそれら部材そのものの破壊（クラック発生）及び基板とヒートシンク間接合界面の脆化クラックの発生を抑制し高信頼性の半導体装置が得らる。さらに、本発明では、ヒートシンクとセラミックス間に従来から存在していた放熱用金属をなくすことができるので構造のシンプル化が達成される。   According to the present invention, a reduction in thermal resistance is achieved mainly by eliminating the heat dissipating metal that has conventionally existed between the heat sink and the ceramic. In addition, when bonding a ceramic substrate and a heat sink metal such as Cu with a solder alloy containing a resin, it is possible to reduce the warpage of the substrate after bonding due to a difference in linear expansion coefficient between the ceramic and the metal, which has been a problem in the past. As a result, the stress generated in the chip and the substrate is reduced, and the highly reliable semiconductor suppresses the destruction (crack generation) of those members themselves and the occurrence of the embrittlement crack at the interface between the substrate and the heat sink by the thermal cycle test. The device is obtained. Furthermore, in the present invention, the heat dissipating metal that has conventionally existed between the heat sink and the ceramic can be eliminated, so that the structure can be simplified.

セラミックス基板に金属板を接合した絶縁回路基板を搭載するＩＧＢＴモジュールなど大電力を使用する半導体装置においては、ＴＣＴやＴＦＴなどの繰り返し試験（熱サイクル試験）の信頼性に優れることが求められていると同時に、チップ特性安定性や熱破壊信頼性の点でチップからヒートシンクにかけての熱抵抗の低減の要求が強く、本発明は、その両特性を両立させるべくなされたものであり、絶縁層たるセラミックス基板とヒートシンクとを直接あるいは接着剤を介して接合されていることを特徴とするものある。以下、実施例を参照して発明の実施の形態を説明する。   Semiconductor devices that use high power, such as IGBT modules that mount an insulating circuit board with a metal plate bonded to a ceramic substrate, are required to have excellent reliability in repeated tests (thermal cycle tests) such as TCT and TFT. At the same time, there is a strong demand for reduction in thermal resistance from the chip to the heat sink in terms of stability of chip characteristics and reliability of thermal destruction, and the present invention has been made in order to achieve both of these characteristics. The substrate and the heat sink are joined directly or via an adhesive. Hereinafter, embodiments of the invention will be described with reference to examples.

まず、図１及び図６、図７を参照して実施例１を説明する。
図１は、本発明のパワー半導体装置（パワーモジュール）の概略断面図、図６は、各実施例及び比較例のパワー半導体装置の特性を示す図、図７は、図１の半導体装置に用いられ、シリコンチップが搭載された回路パターン銅板が形成されているセラミックス基板の斜視図である。本発明のＩＧＢＴモジュールなどパワー半導体装置の絶縁回路部は、例えば、ＤＢＣ基板等が用いられ、セラミックス基板の一方の面（第１の主面）に回路パターン銅板が接合されているが、他方の面（第２の主面）には従来とは異なり放熱用銅板が接合されていない。この回路パターン銅板上に半導体チップを高温はんだによってはんだ付けした後、セラミックス基板をＣｕヒートシンク（Ｃｕベースともいう）上に載置した構造となっている。 First, Embodiment 1 will be described with reference to FIGS. 1, 6, and 7.
FIG. 1 is a schematic cross-sectional view of a power semiconductor device (power module) of the present invention, FIG. 6 is a diagram showing characteristics of power semiconductor devices of each example and comparative example, and FIG. 7 is used for the semiconductor device of FIG. FIG. 2 is a perspective view of a ceramic substrate on which a circuit pattern copper plate on which a silicon chip is mounted is formed. For example, a DBC substrate or the like is used for the insulating circuit portion of the power semiconductor device such as the IGBT module of the present invention, and the circuit pattern copper plate is bonded to one surface (first main surface) of the ceramic substrate. Unlike the conventional case, a heat radiating copper plate is not joined to the surface (second main surface). After the semiconductor chip is soldered on the circuit pattern copper plate with high-temperature solder, the ceramic substrate is placed on a Cu heat sink (also referred to as Cu base).

図１は、ＩＧＢＴモジュールの断面図である。ＩＧＢＴが作り込まれたシリコンチップ１は、セラミックス基板３の第１の主面に形成された回路パターン銅板４上にマウントはんだ７によって接合されている（図７参照）。窒化ケイ素からなるセラミックス基板３は、従来のものとは異なり、第２の主面に放熱用銅板が形成されていない。セラミックス基板３は、Ｃｕヒートシンク２上に載置されている。また、シリコンチップ１と回路パターン銅板４とは、Ａｌなどからなるボンディングワイヤ６によって電気的に接続されている。マウントはんだ７には、例えば、６３Ｓｎ−Ｐｂ系の材料を用いる。本発明において使用されるはんだ合金は、従来から知られている６３Ｓｎ−Ｐｂ系の他に加え、Ｓｎ−Ｃｕ系等のＰｂフリーはんだ合金などを用いても同様の効果が得られる。   FIG. 1 is a cross-sectional view of an IGBT module. The silicon chip 1 in which the IGBT is built is joined to a circuit pattern copper plate 4 formed on the first main surface of the ceramic substrate 3 by a mount solder 7 (see FIG. 7). Unlike the conventional one, the ceramic substrate 3 made of silicon nitride has no heat dissipation copper plate formed on the second main surface. The ceramic substrate 3 is placed on the Cu heat sink 2. The silicon chip 1 and the circuit pattern copper plate 4 are electrically connected by a bonding wire 6 made of Al or the like. For the mount solder 7, for example, a 63Sn—Pb-based material is used. The solder alloy used in the present invention can obtain the same effect by using a Sn-Cu-based Pb-free solder alloy in addition to the conventionally known 63Sn-Pb-based.

シリコンチップ１がマウントされたセラミックス基板３とＣｕヒートシンク２とは直接接触して置かれている。そして、この接触状態は、シリコンチップ１、ヒートシンク２、セラミックス基板３、回路パターン銅板４等を封止するエポキシ樹脂などの材料を用いた樹脂封止体１０を用いて固定される。勿論ヒートシンク２の一面は、樹脂封止体１０から露出している。樹脂封止体１０は、例えば、トランスファーモールド等の方法を用いる。また、セラミックス基板３と回路パターン銅板４とは活性金属法で接合される。活性金属法は、金属と絶縁物との接合方法として知られている。この方法は、まず、セラミックス基板３の上に厚さ３０μｍ程度の鑞剤層３０を形成する。この鑞剤は、例えば、７２Ａｇ−２８Ｃｕからなる基材にその２〜５重量％程度の活性金属であるＴｉなどを含有させて構成されている。鑞剤層上に回路パターン銅板４を載せて８００〜８５０℃程度で加熱すると、鑞剤のＴｉがセラミックス基板３に拡散し、酸化して鑞剤層がセラミックス基板３に強固に接合してセラミックス基板３と回路パターン銅板４とを接合する。   The ceramic substrate 3 on which the silicon chip 1 is mounted and the Cu heat sink 2 are placed in direct contact. And this contact state is fixed using the resin sealing body 10 using materials, such as an epoxy resin, which seals the silicon chip 1, the heat sink 2, the ceramic substrate 3, the circuit pattern copper plate 4, and the like. Of course, one surface of the heat sink 2 is exposed from the resin sealing body 10. The resin sealing body 10 uses, for example, a method such as transfer molding. Further, the ceramic substrate 3 and the circuit pattern copper plate 4 are bonded by an active metal method. The active metal method is known as a method for joining a metal and an insulator. In this method, first, a glaze layer 30 having a thickness of about 30 μm is formed on the ceramic substrate 3. This glaze is constituted, for example, by containing a base material made of 72Ag-28Cu with Ti as an active metal of about 2 to 5% by weight. When the circuit pattern copper plate 4 is placed on the glaze layer and heated at about 800 to 850 ° C., Ti of the glaze diffuses into the ceramic substrate 3 and oxidizes, so that the glaze layer is firmly bonded to the ceramic substrate 3 and ceramics. The substrate 3 and the circuit pattern copper plate 4 are joined.

この半導体装置の熱抵抗評価は、製品使用状態での熱抵抗評価として通常行われているΔｍＶ法により、各組合せを比較した（Ｎ＝３平均）。
モジュール強度信頼性評価として、ＴＣＴ（１サイクル：−４０℃×６０分→ＲＴ．（室温）×５分→１２５℃×６０分→ＲＴ．×５分）３００サイクル後のセラミックス基板でのクラック有無を確認した。また、ＴＣＴ前及びＴＣＴ３００サイクル後のサンプルについて、超音波探傷装置（ＳＡＴ）にてヒートシンク／セラミックス基板間の樹脂ボイド面積率を測定し、その増加量を脆化量として評価した。結果を図６に示す。 For the thermal resistance evaluation of this semiconductor device, the combinations were compared by the ΔmV method that is usually performed as thermal resistance evaluation in the product use state (N = 3 average).
As a module strength reliability evaluation, cracks on the ceramic substrate after 300 cycles of TCT (1 cycle: −40 ° C. × 60 minutes → RT. (Room temperature) × 5 minutes → 125 ° C. × 60 minutes → RT. × 5 minutes) It was confirmed. Moreover, the resin void area ratio between a heat sink / ceramics board | substrate was measured with the ultrasonic flaw detector (SAT) about the sample before TCT and after TCT300 cycles, and the increase amount was evaluated as the amount of embrittlement. The results are shown in FIG.

この実施例によれば、主としてヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことによって、熱抵抗の低減が達成される。また、ヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことができるので構造のシンプル化が達成される。   According to this embodiment, a reduction in thermal resistance is achieved mainly by eliminating the heat-dissipating metal that has conventionally existed between the heat sink and the ceramic substrate. In addition, since the heat dissipating metal that has conventionally existed between the heat sink and the ceramic substrate can be eliminated, the structure can be simplified.

次に、図２及び図６を参照して実施例２を説明する。
図２は、本発明のパワー半導体装置（パワーモジュール）の概略断面図である。この実施例のＩＧＢＴモジュールの絶縁回路部は、例えば、ＤＢＣ基板等が用いられ、セラミックス基板の一方の面（第１の主面）に回路パターン銅板が接合されているが、他方の面（第２の主面）には従来とは異なり放熱用銅板が接合されていない。この回路パターン銅板上に半導体チップを高温はんだによってはんだ付けした後、セラミックス基板をＣｕヒートシンク上に載置した構造となっている。 Next, Embodiment 2 will be described with reference to FIGS.
FIG. 2 is a schematic cross-sectional view of the power semiconductor device (power module) of the present invention. For example, a DBC substrate or the like is used for the insulating circuit portion of the IGBT module of this embodiment, and the circuit pattern copper plate is bonded to one surface (first main surface) of the ceramic substrate. Unlike the prior art, a heat radiating copper plate is not joined to the main surface 2). After the semiconductor chip is soldered on the circuit pattern copper plate with high-temperature solder, the ceramic substrate is placed on a Cu heat sink.

図２は、ＩＧＢＴモジュールの断面図である。ＩＧＢＴが作り込まれたシリコンチップ２１は、窒化ケイ素などからなるセラミックス基板２３の第１の主面にはんだ２９により接合された回路パターン銅板２４の上に、マウントはんだ２７によって接合されている。セラミックス基板２３は、従来のものとは異なり、第２の主面に放熱用銅板が形成されていない。セラミックス基板２３は、リフローはんだ２８によりＣｕヒートシンク２２に接合されている。また、シリコンチップ２１と回路パターン銅板２４とは、Ａｌなどからなるボンディングワイヤ２６によって電気的に接続されている。マウントはんだ２７には、例えば、６３Ｓｎ−Ｐｂ系の材料を用いる。   FIG. 2 is a cross-sectional view of the IGBT module. The silicon chip 21 in which the IGBT is fabricated is joined by a mount solder 27 on a circuit pattern copper plate 24 joined by solder 29 to a first main surface of a ceramic substrate 23 made of silicon nitride or the like. Unlike the conventional one, the ceramic substrate 23 does not have a heat radiating copper plate formed on the second main surface. The ceramic substrate 23 is joined to the Cu heat sink 22 by reflow solder 28. The silicon chip 21 and the circuit pattern copper plate 24 are electrically connected by a bonding wire 26 made of Al or the like. For the mount solder 27, for example, a 63Sn—Pb-based material is used.

この実施例ではセラミックス基板２３とＣｕヒートシンク２２とを接合するリフローはんだ２８及び回路パターン銅板２４とセラミックス基板２３とを接合するはんだ２９は、エポキシ樹脂などの樹脂を含有するはんだ合金を用いている。シリコンチップ２１、ヒートシンク２２、セラミックス基板２３、回路パターン銅板２４等は、エポキシ樹脂などの材料を用いた樹脂封止体（図示を略す）を用いて封止されている。樹脂封止体は、例えば、トランスファーモールド等の方法を用いる。本発明では、このようなパッケージングを用いずに、ケースでヒートシンクとジョイニング後内部にシリコーンゲルを封入した構造を採用することもできる。この半導体装置の熱抵抗評価、モジュール強度信頼性評価、脆化量評価は、結果を図６に示す。   In this embodiment, the reflow solder 28 for joining the ceramic substrate 23 and the Cu heat sink 22 and the solder 29 for joining the circuit pattern copper plate 24 and the ceramic substrate 23 use a solder alloy containing a resin such as an epoxy resin. The silicon chip 21, the heat sink 22, the ceramic substrate 23, the circuit pattern copper plate 24, and the like are sealed using a resin sealing body (not shown) using a material such as an epoxy resin. For the resin sealing body, for example, a method such as transfer molding is used. In the present invention, without using such packaging, it is possible to adopt a structure in which a silicone gel is sealed inside after heat sink and joining in the case. The results of thermal resistance evaluation, module strength reliability evaluation, and embrittlement amount evaluation of this semiconductor device are shown in FIG.

この実施例によれば、主としてヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことによって、熱抵抗の低減が達成される。また、ヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことができるので構造のシンプル化が達成される。また、セラミックス基板とＣｕ等のヒートシンク金属とは樹脂を含むはんだ合金で接合されているので、はんだに含まれる樹脂の塑性変形を吸収する作用により、従来より問題となっていたセラミックスと金属との線膨張係数差に起因する接合後の基板反りを低減でき、その結果、チップ、セラミックス基板に発生する応力低減が図られ、熱サイクル試験によるそれら部材そのものの破壊（クラック発生）及びセラミックス基板とヒートシンク間接合界面の脆化クラックの発生を抑制して高信頼性の半導体装置が得られる。   According to this embodiment, a reduction in thermal resistance is achieved mainly by eliminating the heat-dissipating metal that has conventionally existed between the heat sink and the ceramic substrate. In addition, since the heat dissipating metal that has conventionally existed between the heat sink and the ceramic substrate can be eliminated, the structure can be simplified. In addition, since the ceramic substrate and the heat sink metal such as Cu are joined by a solder alloy containing a resin, the action of absorbing the plastic deformation of the resin contained in the solder, the ceramic and the metal that have been problematic in the past Substrate warpage after bonding due to the difference in linear expansion coefficient can be reduced. As a result, the stress generated in the chip and the ceramic substrate can be reduced, the member itself is destroyed (crack generation) by the thermal cycle test, and the ceramic substrate and the heat sink. A highly reliable semiconductor device can be obtained by suppressing the occurrence of embrittlement cracks at the inter-bonding interface.

次に、図３及び図６を参照して実施例３を説明する。
図３は、本発明のパワー半導体装置（パワーモジュール）の概略断面図である。この実施例のＩＧＢＴモジュールの絶縁回路部は、例えば、ＤＢＣ基板等が用いられ、窒化ケイ素などからなるセラミックス基板の一方の面（第１の主面）に回路パターン銅板が接合されているが、他方の面（第２の主面）には従来とは異なり放熱用銅板が接合されていない。この回路パターン銅板上に半導体チップを高温はんだによってはんだ付けした後、セラミックス基板をＣｕヒートシンク（Ｃｕベースともいう）上に載置した構造となっている。 Next, Embodiment 3 will be described with reference to FIGS.
FIG. 3 is a schematic cross-sectional view of the power semiconductor device (power module) of the present invention. The insulation circuit portion of the IGBT module of this embodiment is, for example, a DBC substrate or the like, and a circuit pattern copper plate is joined to one surface (first main surface) of a ceramic substrate made of silicon nitride or the like. Unlike the prior art, a heat radiating copper plate is not joined to the other surface (second main surface). After the semiconductor chip is soldered on the circuit pattern copper plate with high-temperature solder, the ceramic substrate is placed on a Cu heat sink (also referred to as Cu base).

図３は、ＩＧＢＴモジュールの断面図である。ＩＧＢＴが作り込まれたシリコンチップ３１は、セラミックス基板３３の第１の主面に形成された回路パターンを構成するメタライズ層３４上にマウントはんだ３７によって接合されている。メタライズ層３４は、セラミックス基板３３上に回路パターン状に導電ペーストを塗布し、これを熱処理して形成する膜厚５０〜８０μｍの厚膜パターンである。厚膜パターンを構成する金属材料にはＭｏ−ＴｉＮ、Ｗなどが用いられる。セラミックス基板３３は、従来のものとは異なり、第２の主面に放熱用銅板が形成されていない。セラミックス基板３３は、Ｃｕヒートシンク３２上に載置されている。また、シリコンチップ３１とメタライズ層３４とは、Ａｌなどからなるボンディングワイヤ３６によって電気的に接続されている。マウントはんだ３７には、例えば、６３Ｓｎ−Ｐｂ系の材料を用いる。   FIG. 3 is a cross-sectional view of the IGBT module. The silicon chip 31 in which the IGBT is built is joined by a mount solder 37 on a metallized layer 34 constituting a circuit pattern formed on the first main surface of the ceramic substrate 33. The metallized layer 34 is a thick film pattern with a film thickness of 50 to 80 μm formed by applying a conductive paste in a circuit pattern on the ceramic substrate 33 and heat-treating it. Mo-TiN, W, etc. are used for the metal material which comprises a thick film pattern. Unlike the conventional one, the ceramic substrate 33 does not have a heat radiating copper plate formed on the second main surface. The ceramic substrate 33 is placed on the Cu heat sink 32. The silicon chip 31 and the metallized layer 34 are electrically connected by a bonding wire 36 made of Al or the like. For the mount solder 37, for example, a 63Sn—Pb-based material is used.

セラミックス基板３３とＣｕヒートシンク３２とは、エポキシ樹脂を含有するはんだ合金（リフローはんだ３８）により接合されている。シリコンチップ３１、ヒートシンク３２、セラミックス基板３３、メタライズ層３４等は、エポキシ樹脂などの材料を用いた樹脂封止体（図示を略す）を用いて封止されている。樹脂封止体は、例えば、トランスファーモールド等の方法を用いる。本発明では、このようなパッケージングを用いずに、ケースでヒートシンクとジョイニング後内部にシリコーンゲルを封入した構造を採用することもできる。この半導体装置の熱抵抗評価、モジュール強度信頼性評価、脆化量評価は、結果を図６に示す。   The ceramic substrate 33 and the Cu heat sink 32 are joined by a solder alloy (reflow solder 38) containing an epoxy resin. The silicon chip 31, the heat sink 32, the ceramic substrate 33, the metallized layer 34, and the like are sealed using a resin sealing body (not shown) using a material such as an epoxy resin. For the resin sealing body, for example, a method such as transfer molding is used. In the present invention, without using such packaging, it is possible to adopt a structure in which a silicone gel is sealed inside after heat sink and joining in the case. The results of thermal resistance evaluation, module strength reliability evaluation, and embrittlement amount evaluation of this semiconductor device are shown in FIG.

この実施例によれば、主としてヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことによって、熱抵抗の低減が達成される。また、ヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことができるので構造のシンプル化が達成される。また、セラミックス基板とＣｕ等のヒートシンク金属とは樹脂を含むはんだ合金で接合されているので、従来より問題となっていたセラミックス基板と金属との線膨張係数差に起因する接合後の基板反りを低減でき、その結果、チップ、基板に発生する応力低減が図られ、熱サイクル試験によるそれら部材そのものの破壊（クラック発生）及び基板とヒートシンク間接合界面の脆化クラックの発生を抑制して高信頼性の半導体装置が得られる。   According to this embodiment, a reduction in thermal resistance is achieved mainly by eliminating the heat-dissipating metal that has conventionally existed between the heat sink and the ceramic substrate. In addition, since the heat dissipating metal that has conventionally existed between the heat sink and the ceramic substrate can be eliminated, the structure can be simplified. In addition, since the ceramic substrate and the heat sink metal such as Cu are bonded with a solder alloy containing a resin, the warpage of the substrate after bonding due to the difference in the linear expansion coefficient between the ceramic substrate and the metal, which has been a problem in the past, has occurred. As a result, the stress generated in the chip and the substrate can be reduced, and high reliability is achieved by suppressing the destruction of those members themselves (crack generation) by the thermal cycle test and the occurrence of embrittlement cracks at the interface between the substrate and the heat sink A semiconductor device is obtained.

次に、図４及び図６を参照して実施例４を説明する。
図４は、本発明のパワー半導体装置（パワーモジュール）の概略断面図である。この実施例のＩＧＢＴモジュールの絶縁回路部は、例えば、ＤＢＣ基板等が用いられ、窒化ケイ素などからなるセラミックス基板の一方の面（第１の主面）に回路パターン銅板が接合されているが、他方の面（第２の主面）には従来とは異なり放熱用銅板が接合されていない。この実施例は、この回路パターン銅板上に半導体チップを高温はんだによってはんだ付けした後、セラミックス基板をＣｕヒートシンク上に載置した構造となっている。 Next, Embodiment 4 will be described with reference to FIGS.
FIG. 4 is a schematic cross-sectional view of the power semiconductor device (power module) of the present invention. The insulation circuit portion of the IGBT module of this embodiment is, for example, a DBC substrate or the like, and a circuit pattern copper plate is joined to one surface (first main surface) of a ceramic substrate made of silicon nitride or the like. Unlike the prior art, a heat radiating copper plate is not joined to the other surface (second main surface). In this embodiment, a semiconductor chip is soldered on this circuit pattern copper plate with high-temperature solder, and then a ceramic substrate is placed on a Cu heat sink.

図４は、ＩＧＢＴモジュールの断面図である。ＩＧＢＴが作り込まれたシリコンチップ４１は、セラミックス基板４３の第１の主面に形成された回路パターンを構成する厚さ０．６〜１．０程度のＣｕフレーム４４上にマウントはんだ４７によって接合されている。フレーム４４は、セラミックス基板４３の第１の主面上に形成さたメタライズ層５０上にはんだ４９により固着されている。セラミックス基板４３は、従来のものとは異なり、第２の主面に放熱用銅板が形成されていない。また、セラミックス基板４３は、Ｃｕヒートシンク４２上に載置され、リフローはんだ４８により固定されている。また、シリコンチップ４１とＣｕフレーム４４とは、Ａｌなどからなるボンディングワイヤ４６によって電気的に接続されている。マウントはんだ４７には、例えば、６３Ｓｎ−Ｐｂ系の材料を用いる。   FIG. 4 is a cross-sectional view of the IGBT module. The silicon chip 41 in which the IGBT is built is joined by a mount solder 47 on a Cu frame 44 having a thickness of about 0.6 to 1.0 constituting a circuit pattern formed on the first main surface of the ceramic substrate 43. Has been. The frame 44 is fixed to the metallized layer 50 formed on the first main surface of the ceramic substrate 43 with solder 49. Unlike the conventional one, the ceramic substrate 43 does not have a heat dissipation copper plate formed on the second main surface. The ceramic substrate 43 is placed on the Cu heat sink 42 and fixed by reflow solder 48. The silicon chip 41 and the Cu frame 44 are electrically connected by a bonding wire 46 made of Al or the like. For the mount solder 47, for example, a 63Sn—Pb-based material is used.

セラミックス基板４３とＣｕヒートシンク４２はエポキシ樹脂を含有するはんだ合金（リフローはんだ４８）により接合されている。シリコンチップ４１、ヒートシンク４２、セラミックス基板４３、メタライズ層４４等は、エポキシ樹脂などの材料を用いた樹脂封止体（図示を略す）を用いて封止されている。樹脂封止体は、例えば、トランスファーモールド等の方法を用いる。この半導体装置の熱抵抗評価、モジュール強度信頼性評価、脆化量評価は、結果を図６に示す。   The ceramic substrate 43 and the Cu heat sink 42 are joined by a solder alloy (reflow solder 48) containing an epoxy resin. The silicon chip 41, the heat sink 42, the ceramic substrate 43, the metallized layer 44, and the like are sealed using a resin sealing body (not shown) using a material such as an epoxy resin. For the resin sealing body, for example, a method such as transfer molding is used. The results of thermal resistance evaluation, module strength reliability evaluation, and embrittlement amount evaluation of this semiconductor device are shown in FIG.

この実施例によれば、主としてヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことによって、熱抵抗の低減が達成される。また、ヒートシンクとセラミックス基板間に従来から存在していた放熱用金属をなくすことができるので構造のシンプル化が達成される。また、セラミックス基板とＣｕ等のヒートシンク金属とは樹脂を含むはんだ合金で接合されているので、従来より問題となっていたセラミックス基板と金属との線膨張係数差に起因する接合後の基板反りを低減でき、その結果、チップ、基板に発生する応力低減が図られ、熱サイクル試験によるそれら部材そのものの破壊（クラック発生）及び基板とヒートシンク間接合界面の脆化クラックの発生を抑制し高信頼性の半導体装置が得られる。また、メタライズ層及びフレームを用いることにより熱抵抗が低減され、しかも安価にこの様な半導体装置を形成することができる。   According to this embodiment, a reduction in thermal resistance is achieved mainly by eliminating the heat-dissipating metal that has conventionally existed between the heat sink and the ceramic substrate. In addition, since the heat dissipating metal that has conventionally existed between the heat sink and the ceramic substrate can be eliminated, the structure can be simplified. In addition, since the ceramic substrate and the heat sink metal such as Cu are bonded with a solder alloy containing a resin, the warpage of the substrate after bonding due to the difference in the linear expansion coefficient between the ceramic substrate and the metal, which has been a problem in the past, has occurred. As a result, the stress generated in the chip and the substrate can be reduced, and the thermal cycle test can suppress the destruction of these components themselves (cracking) and the occurrence of embrittlement cracks at the interface between the substrate and the heat sink. The semiconductor device can be obtained. Further, by using the metallized layer and the frame, the thermal resistance is reduced, and such a semiconductor device can be formed at a low cost.

次に、実施例５乃至実施例１１を説明する。
図６は、ヒートシンク厚さ、セラミックス基板厚さ、ヒートシンク金属材料、はんだ合金材料を種々変えた場合における各実施例（実施例１乃至実施例１１）及び比較例（比較例１乃至比較例４）のパワー半導体装置の特性を示すものである。図番は、実施例に対応する図１〜５のいずれかを示す。セラミックスは、セラミックス基板材料を示す。熱伝導率κ（Ｗ／ｍＫ）は、セラミックス基板の熱伝導を示す。セラミックス厚さ（ｍｍ）は、セラミックス基板の厚さを示す。ヒートシンク金属は、ヒートシンク材料を示す。熱抵抗Ｒth（℃／Ｗ）は、パワー半導体装置の使用状態での熱抵抗評価を示す。ＴＣＴ後クラック有無は、パワー半導体装置の強度信頼性評価を示す。ＴＣＴ後はんだ脆化量（％）は、パワー半導体装置の脆化量を示す。 Next, Examples 5 to 11 will be described.
FIG. 6 shows each example (Example 1 to Example 11) and comparative example (Comparative Example 1 to Comparative Example 4) when the heat sink thickness, the ceramic substrate thickness, the heat sink metal material, and the solder alloy material are variously changed. The characteristics of this power semiconductor device are shown. The figure number indicates any one of FIGS. 1 to 5 corresponding to the embodiment. Ceramics refers to a ceramic substrate material. The thermal conductivity κ (W / mK) indicates the thermal conductivity of the ceramic substrate. The ceramic thickness (mm) indicates the thickness of the ceramic substrate. Heat sink metal refers to a heat sink material. Thermal resistance Rth (° C./W) indicates thermal resistance evaluation in a usage state of the power semiconductor device. The presence or absence of cracks after TCT indicates the strength reliability evaluation of the power semiconductor device. The post-TCT solder embrittlement amount (%) indicates the amount of embrittlement of the power semiconductor device.

実施例１乃至実施例４は、それぞれ各図１乃至図４に示すパワー半導体装置を用いている。実施例５乃至実施例１１は、図１に示すパワー半導体装置を用いている。比較例１乃至比較例４は、図５に示す従来のパワー半導体装置を用いている。各実施例及び比較例で用いられるセラミックス基板の材料は、実施例１乃至実施例１１及び比較例１，２が窒化珪素であり、比較例３が窒化アルミニウムであり、比較例４は、アルミナを用いている。
図６において、熱抵抗Ｒthをみると、実施例では比較例１，２，４より１０〜２０％程度低減されている。また、熱抵抗的に実施例と同等の特性を有する比較例３のサンプルでは、実施例では見られなかったＴＣＴ後でのクラックが見られたので、本発明は総合的に比較例より優れた作用効果が認められる。 In the first to fourth embodiments, the power semiconductor devices shown in FIGS. 1 to 4 are used. In the fifth to eleventh embodiments, the power semiconductor device shown in FIG. 1 is used. Comparative Examples 1 to 4 use the conventional power semiconductor device shown in FIG. The materials of the ceramic substrate used in each example and comparative example are silicon nitride in Examples 1 to 11 and Comparative Examples 1 and 2, Comparative Example 3 is aluminum nitride, and Comparative Example 4 is alumina. Used.
In FIG. 6, the thermal resistance Rth is reduced by about 10 to 20% in the example compared with the comparative examples 1, 2, and 4. Further, in the sample of Comparative Example 3 having the same thermal resistance as that of the Example, cracks after TCT that were not seen in the Example were observed, so the present invention was comprehensively superior to the Comparative Example. The effect is recognized.

本発明を説明する実施例は、以上の通りであるが、本発明は、さらに次のような構造を有することができる。セラミックス基板上に形成された回路パターン銅板の厚さは、１００μｍが適当である。Ｃｕなどのヒートシンクの厚さは、２ｍｍ以上が適当である。セラミックス基板の厚さは、０．５５ｍｍ以下が適当であるである。ヒートシンク金属は、Ｃｕの外、Ａｌであってもよい。ヒートシンクは、ＣｕあるいはＡｌを含む複合体であってもよい。セラミックス基板とヒートシンクとの接合に用いられる合金、もしくは半導体チップと回路パターンを接合するはんだは、Ｐｂフリーであってもよい。   The embodiments illustrating the present invention are as described above, but the present invention can further have the following structure. The thickness of the circuit pattern copper plate formed on the ceramic substrate is suitably 100 μm. The thickness of the heat sink such as Cu is suitably 2 mm or more. The thickness of the ceramic substrate is suitably 0.55 mm or less. The heat sink metal may be Al in addition to Cu. The heat sink may be a composite containing Cu or Al. The alloy used for joining the ceramic substrate and the heat sink, or the solder joining the semiconductor chip and the circuit pattern may be Pb-free.

本発明の実施例１に係る半導体装置（パワーモジュール）の概略断面図。1 is a schematic cross-sectional view of a semiconductor device (power module) according to Embodiment 1 of the present invention. 本発明の実施例２に係る半導体装置（パワーモジュール）の概略断面図。FIG. 6 is a schematic cross-sectional view of a semiconductor device (power module) according to Example 2 of the invention. 本発明の実施例３に係る半導体装置（パワーモジュール）の概略断面図。FIG. 6 is a schematic cross-sectional view of a semiconductor device (power module) according to Example 3 of the invention. 本発明の実施例４に係る半導体装置（パワーモジュール）の概略断面図。FIG. 6 is a schematic cross-sectional view of a semiconductor device (power module) according to Example 4 of the invention. 従来の半導体装置（パワーモジュール）の概略断面図。FIG. 6 is a schematic cross-sectional view of a conventional semiconductor device (power module). 各実施例及び比較例の半導体装置の特性を示す図。The figure which shows the characteristic of the semiconductor device of each Example and a comparative example. 図１の半導体装置において用いられるセラミックス基板の平面図。The top view of the ceramic substrate used in the semiconductor device of FIG.

符号の説明Explanation of symbols

１、２１、３１、４１、１０１・・・シリコンチップ
２、２２、３２、４２、１０２・・・ヒートシンク
３、２３、３３、４３、１０３・・・セラミックス基板
４、２４、１０４・・・回路パターン銅板
６、２６、３６、４６、１０６・・・ボンディングワイヤ
７、２７、３７、４７、１０７・・・マウントはんだ
１０・・・樹脂封止体
２８、３８、４８、１０８・・・リフローはんだ
２９、４９・・・はんだ
３４、５０・・・メタライズ層
４４・・・Ｃｕフレーム
１０５・・・放熱用銅板 1, 21, 31, 41, 101 ... Silicon chip 2, 22, 32, 42, 102 ... Heat sink 3, 23, 33, 43, 103 ... Ceramic substrate 4, 24, 104 ... Circuit Pattern copper plate 6, 26, 36, 46, 106 ... Bonding wire 7, 27, 37, 47, 107 ... Mount solder 10 ... Resin encapsulant 28, 38, 48, 108 ... Reflow solder 29, 49 ... solder 34, 50 ... metallized layer 44 ... Cu frame 105 ... heat dissipation copper plate

Claims (5)

半導体チップと、
前記半導体チップが第１の主面上に搭載されたセラミックス基板と、
前記半導体チップが接合されている前記第１の主面に形成された回路パターンと、
前記セラミックス基板の第１の主面とは反対側の第２の主面に直接接しているヒートシンクとを備えていることを特徴とする半導体装置。 A semiconductor chip;
A ceramic substrate on which the semiconductor chip is mounted on the first main surface;
A circuit pattern formed on the first main surface to which the semiconductor chip is bonded;
A semiconductor device comprising: a heat sink directly in contact with a second main surface opposite to the first main surface of the ceramic substrate. 半導体チップと、
前記半導体チップが第１の主面上に搭載されたセラミックス基板と、
前記半導体チップが接合された第１の主面に形成された回路パターンと、
前記セラミックス基板の第１の主面とは反対側の第２の主面に接着剤を介して接しているヒートシンクとを備えていることを特徴とする半導体装置。 A semiconductor chip;
A ceramic substrate on which the semiconductor chip is mounted on the first main surface;
A circuit pattern formed on the first main surface to which the semiconductor chip is bonded;
A semiconductor device comprising: a heat sink in contact with a second main surface opposite to the first main surface of the ceramic substrate through an adhesive. 前記セラミックス基板と前記ヒートシンクとが樹脂を含有するはんだ合金により接合されていることを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the ceramic substrate and the heat sink are joined by a solder alloy containing a resin. 前記セラミックス基板と前記ヒートシンクの側面は、絶縁性樹脂層により被覆されていることを特徴とする請求項１又は請求項２に記載の半導体装置。 The semiconductor device according to claim 1, wherein side surfaces of the ceramic substrate and the heat sink are covered with an insulating resin layer. 前記セラミックス基板は、窒化ケイ素からなることを特徴とする請求項１乃至請求項４のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the ceramic substrate is made of silicon nitride.
JP2004094135A 2004-03-29 2004-03-29 Semiconductor device Pending JP2005285885A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008028011A (en) * 2006-07-19 2008-02-07 Denso Corp Mold package, and its manufacturing method
WO2012068777A1 (en) * 2010-11-22 2012-05-31 复旦大学 Method of fabricating semiconductor substrate for fabricating high power device
JP2012114224A (en) * 2010-11-24 2012-06-14 Mitsubishi Materials Corp Power module substrate with heat sink and manufacturing method of the power module and the power module substrate
US11439039B2 (en) 2020-12-07 2022-09-06 Hamilton Sundstrand Corporation Thermal management of electronic devices on a cold plate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008028011A (en) * 2006-07-19 2008-02-07 Denso Corp Mold package, and its manufacturing method
WO2012068777A1 (en) * 2010-11-22 2012-05-31 复旦大学 Method of fabricating semiconductor substrate for fabricating high power device
JP2012114224A (en) * 2010-11-24 2012-06-14 Mitsubishi Materials Corp Power module substrate with heat sink and manufacturing method of the power module and the power module substrate
US11439039B2 (en) 2020-12-07 2022-09-06 Hamilton Sundstrand Corporation Thermal management of electronic devices on a cold plate

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