JP2919651B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP2919651B2 JP2919651B2 JP3188861A JP18886191A JP2919651B2 JP 2919651 B2 JP2919651 B2 JP 2919651B2 JP 3188861 A JP3188861 A JP 3188861A JP 18886191 A JP18886191 A JP 18886191A JP 2919651 B2 JP2919651 B2 JP 2919651B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- insulating resin
- integrated circuit
- hybrid integrated
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路に関し、特
にパワー素子が搭載された混成集積回路の改良に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly, to an improvement of a hybrid integrated circuit on which a power element is mounted.
【０００２】[0002]
【従来の技術】従来の混成集積回路を図４に示す。混成
集積回路基板（２１）は表面をアルマイト処理したアル
ミニウム基板を用い、基板（２１）上に絶縁樹脂層を介
して所望形状の導電路（２２）が形成されている。かか
る導電路（２２）上あるいは導電路（２２）間に半導体
チップ、チップコンデンサー及び印刷抵抗体等の回路素
子（２３）が搭載され、導電路（２２）を介して相互接
続されている。尚、図示されないが導電路（２２）は基
板（２１）に貼着されたエポキシ樹脂等の絶縁性接着剤
層を介して形成されている。2. Description of the Related Art A conventional hybrid integrated circuit is shown in FIG. As the hybrid integrated circuit board (21), an aluminum substrate whose surface is anodized is used, and a conductive path (22) having a desired shape is formed on the board (21) via an insulating resin layer. Circuit elements (23) such as semiconductor chips, chip capacitors, and printed resistors are mounted on or between the conductive paths (22), and are interconnected via the conductive paths (22). Although not shown, the conductive path (22) is formed via an insulating adhesive layer such as an epoxy resin adhered to the substrate (21).
【０００３】上述した混成集積回路は一般的に小電力用
に用いられる。これは、基板（２１）上に絶縁樹脂層
（図示しない）を介して回路形成されるため熱抵抗が大
きくなるからである。そこで、かかる混成集積回路構造
の絶縁樹脂層中にアルミナ、シリカ、ボロン等のフィラ
ーを含有させて熱抵抗を小さくした混成集積回路が種々
提案されている。従って、大出力用あるいは大出力回路
とその周辺の小信号回路を有する混成集積回路にあって
は、一般的に熱抵抗を優先させたフィラー入り樹脂層を
有した基板上にそれらの回路が形成される。The above-mentioned hybrid integrated circuit is generally used for low power. This is because the circuit is formed on the substrate (21) via an insulating resin layer (not shown), so that the thermal resistance increases. Therefore, various hybrid integrated circuits have been proposed in which the insulating resin layer of such a hybrid integrated circuit structure contains a filler such as alumina, silica, or boron to reduce the thermal resistance. Therefore, in the case of a hybrid integrated circuit having a large output circuit or a large output circuit and a small signal circuit around the circuit, the circuits are generally formed on a substrate having a resin layer containing a filler in which thermal resistance is prioritized. Is done.
【０００４】[0004]
【発明が解決しようとする課題】斯上した混成集積回路
上に搭載されるチップ抵抗、チップコンデンサー等のチ
ップ部品は一般に半田で導電路上に接続されているため
に以下の問題が発生する。即ち、アルミニウム基板をベ
ース基板とした基板の熱膨張係数αが２３×１０ -6／℃
であり、上記したチップ部品、例えばチップ抵抗の熱膨
張係数αが７×１０-6／℃、チップコンデンサーの熱膨
張係数αが１０×１０-6／℃であるため両者の膨張係数
αが著しく異なるために温度サイクルによってチップ部
品と導電路を接続する半田固着部分に温度サイクルによ
るストレスが加わり、半田固着部分にクラックが発生し
接続不良となる問題がある。SUMMARY OF THE INVENTION Such a hybrid integrated circuit is disclosed.
Chip resistors, chip capacitors, etc.
Components are generally connected to conductive paths with solder.
The following problems occur. That is, the aluminum substrate is
Substrate has a thermal expansion coefficient α of 23 × 10 -6/ ℃
And thermal expansion of the above-mentioned chip component, for example, a chip resistor.
The tension coefficient α is 7 × 10-6/ ℃, thermal expansion of chip capacitor
Tensile coefficient α is 10 × 10-6/ ° C, the expansion coefficient of both
Since the α is significantly different, the chip
Temperature cycle at the soldered part connecting the product and the conductive path.
Stress is applied, and cracks occur
There is a problem of poor connection.
【０００５】次にクラックが発生するメカニズムについ
て説明する。上記したようにアルミニウム基板の膨張係
数αが２３×１０-6／℃、チップ部品の膨張係数αが７
〜１０×１０-6／℃であり、チップ部品を接合する半田
の膨張係数αが約２３×１０ -6／℃であるため、室温状
態では図５のＡの如く、基板、半田、チップ部に応力が
加わらない。しかし、高温状態では図５のＢの如く、基
板と半田のαがチップ部品より大きいため矢印方向に引
張られ、その結果、接合半田は矢印の方向にのみすそが
広がるように変形する。又、低温状態では図５のＣに示
す如く、反対の矢印方向に圧縮力が加えられその結果、
接合半田は矢印方向にのみすそが広がる。例えば、−５
０〜＋１５０℃の条件の厳しい温度サイクル条件で数十
〜数百サイクルくり返すことにより、上述したようにα
の著しく異なるチップ部品と半田の接合面にクラックが
発生する。何故なら、温度サイクルにより微結晶状態に
ある半田成分のスズと鉛成分が分離し凝集して半田内に
連続的な鉛層を形成するため機械的強度を低下させるか
らである。Next, the mechanism of crack generation will be described.
Will be explained. As described above, the expansion of the aluminum substrate
Number α is 23 × 10-6/ ° C, expansion coefficient α of chip parts is 7
-10 × 10-6/ ° C, solder for joining chip components
Of about 23 × 10 -6/ ° C, room temperature
In this state, as shown in FIG.
Will not join. However, in the high temperature state, as shown in FIG.
Since the α of the board and solder is larger than the chip component, pull in the direction of the arrow.
As a result, the bonding solder is skirted only in the direction of the arrow.
Deform to spread. In the low temperature state, it is shown in FIG.
As such, a compressive force is applied in the opposite arrow direction, and as a result,
The solder spreads only in the direction of the arrow. For example, -5
Dozens of times under severe temperature cycle conditions of 0 to + 150 ° C
By repeating a few hundred cycles, as described above, α
Cracks on the joining surface of chip components and solder
Occur. Because the temperature cycle makes it into a microcrystalline state
Tin and lead components of a certain solder component are separated and aggregated into the solder.
Do you reduce mechanical strength to form a continuous lead layer?
It is.
【０００６】上述した問題は金属基板、特にアルミニウ
ム基板をベースとした集積回路特有の問題であり、プリ
ント基板等の他の基板をベースとした集積回路では問題
にならない。何故なら、そのようなベース基板であって
はチップ部品あるいは印刷抵抗体の膨張係数αと基板の
膨張係数αの差による上述した問題が発生しないからで
ある。The above-mentioned problem is a problem peculiar to an integrated circuit based on a metal substrate, particularly an aluminum substrate, and does not become a problem in an integrated circuit based on another substrate such as a printed circuit board. This is because such a base substrate does not cause the above-described problem due to the difference between the expansion coefficient α of the chip component or the printed resistor and the expansion coefficient α of the substrate.
【０００７】[0007]
【課題を解決するための手段】本発明は、上述した課題
に鑑みて為されたものであり、金属基板上に絶縁樹脂層
を介して形成された導電路上にパワー半導体素子及び他
の回路素子が固着された混成集積回路において、前記パ
ワー半導体素子は所望重量比のフィラーが混入された低
熱抵抗樹脂層上に搭載され、前記他の回路素子は延性特
性を有した絶縁樹脂層上に搭載されたことを特徴とす
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and has a power semiconductor element and other circuit elements on a conductive path formed on a metal substrate via an insulating resin layer. In the hybrid integrated circuit to which is fixed, the power semiconductor element is mounted on a low thermal resistance resin layer mixed with a filler of a desired weight ratio, and the other circuit element is mounted on an insulating resin layer having ductility characteristics. It is characterized by having.
【０００８】また、前記延性特性を有する絶縁樹脂層は
前記低熱抵抗樹脂層上に設けられていることを特徴とす
る。また、前記他の回路素子として、チップ抵抗あるい
はチップコンデンサーを用いたことを特徴とする。ま
た、前記延性特性を有した絶縁樹脂層としてポリイミド
樹脂を用いたことを特徴とする。[0008] The insulating resin layer having the ductility characteristic is provided on the low heat resistance resin layer. Further, a chip resistor or a chip capacitor is used as the other circuit element. Further, a polyimide resin is used as the insulating resin layer having the ductility characteristic.
【０００９】[0009]
【作用】以上のように構成される混成集積回路において
は、パワー半導体素子が低熱抵抗樹脂層上に搭載され、
それ以外の他の回路素子、例えばチップ抵抗、チップコ
ンデンサー等のチップ部分は延性特性を有する絶縁樹脂
層上に搭載された構造となるために、混成集積回路の使
用等により、厳しい条件下の温度サイクルが生じたとし
ても延性特性を有する絶縁樹脂層上に搭載されたチップ
抵抗、チップコンデンサー等のチップ部品状の回路素子
にあっては、温度サイクルにより生じるチップ部品の半
田接合部のストレスは延性特性を有する絶縁樹脂層によ
って緩和することができる。In the hybrid integrated circuit configured as described above, the power semiconductor element is mounted on the low thermal resistance resin layer,
Other circuit elements, such as chip parts such as chip resistors and chip capacitors, have a structure mounted on an insulating resin layer with ductility characteristics. Even if a cycle occurs, in the case of chip components such as chip resistors and chip capacitors mounted on an insulating resin layer that has ductility characteristics, the stress of the solder joint of the chip component caused by the temperature cycle is ductile. It can be alleviated by an insulating resin layer having characteristics.
【００１０】[0010]
【実施例】以下に図１に示した実施例に基づいて本発明
の混成集積回路を説明する。図１は本発明の混成集積回
路を示す要部拡大断面図であり、（１）は金属基板、
（２）は第１の絶縁樹脂層、（３）は導電路、（４）は
チップ抵抗、チップコンデンサー等のチップ部品、
（５）は第２の絶縁樹脂層、（６）はパワー半導体素子
である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A hybrid integrated circuit according to the present invention will be described below with reference to the embodiment shown in FIG. FIG. 1 is an enlarged sectional view of a main part showing a hybrid integrated circuit of the present invention.
(2) a first insulating resin layer, (3) a conductive path, (4) a chip component such as a chip resistor and a chip capacitor,
(5) is a second insulating resin layer, and (6) is a power semiconductor element.
【００１１】金属基板（１）としては、例えば、アルミ
ニウム基板あるいはアルミニウム基板表面をアルマイト
処理したものを用い、ここでは後者のアルミニウム基板
を用いるものとする。その基板（１）の一主面上には絶
縁樹脂層を介して所望形状の導電路が形成され、その導
電路上に種々の回路素子が固着搭載される。さて、本発
明においては基板（１）上に材質の異なる二種類の絶縁
樹脂層（２）（５）が存在する。即ち、パワートランジ
スタ等のパワー半導体素子（６）が搭載される第１の絶
縁樹脂層（２）とパワー半導体素子（６）以外の回路素
子（４）が搭載される第２の絶縁樹脂層（５）を有す
る。As the metal substrate (1), for example, an aluminum substrate or a substrate obtained by subjecting the surface of an aluminum substrate to alumite treatment is used. Here, the latter aluminum substrate is used. A conductive path having a desired shape is formed on one main surface of the substrate (1) via an insulating resin layer, and various circuit elements are fixedly mounted on the conductive path. Now, in the present invention, two types of insulating resin layers (2) and (5) having different materials exist on the substrate (1). That is, a first insulating resin layer (2) on which a power semiconductor element (6) such as a power transistor is mounted and a second insulating resin layer (2) on which a circuit element (4) other than the power semiconductor element (6) is mounted 5).
【００１２】第１の絶縁樹脂層（２）はパワー半導体素
子（６）の熱放散を向上させるために低熱抵抗タイプの
絶縁樹脂層が用いられている。かかる第１の絶縁樹脂層
（２）は、例えばエポキシ樹脂、フェノール樹脂、キシ
レン樹脂等の樹脂中に、所定重量比、例えば３０〜８０
％の割合のＢｅＯ，ＭｇＯ，Ａｌ2Ｏ3等の酸化物セラミ
ックス，ＡＩＮ，ＢＮ等の窒化物セラミックスの所定粒
径のフィラーが混入されており、第１の絶縁樹脂層
（２）の熱抵抗を低く設定している。As the first insulating resin layer (2), a low thermal resistance type insulating resin layer is used in order to improve heat dissipation of the power semiconductor element (6). Such a first insulating resin layer (2) is formed in a resin such as an epoxy resin, a phenol resin, or a xylene resin in a predetermined weight ratio, for example, 30 to 80.
% Of oxide ceramics such as BeO, MgO, and Al 2 O 3 , and nitride ceramics such as AIN and BN having a predetermined particle size, and the thermal resistance of the first insulating resin layer (2). Is set low.
【００１３】一方、第２の絶縁樹脂層（５）はヒートサ
イクル時に基板（１）と第２の絶縁樹脂層（５）上に搭
載する回路素子（４）の熱膨張率αの差によるストレス
を吸収緩和できる延性特性を有する絶縁樹脂層が用いら
れる。第２の絶縁樹脂層（５）としてカプトン（商品
名）等のポリイミド樹脂が用いられる。かかるポリイミ
ド樹脂の延性特性は約８０〜８５％位有し、十分にヒー
トサイクルによるストレスを吸収緩和できるものであ
る。On the other hand, during the heat cycle, the second insulating resin layer (5) is subjected to stress caused by the difference in the coefficient of thermal expansion α between the substrate (1) and the circuit element (4) mounted on the second insulating resin layer (5). An insulating resin layer having a ductile property capable of absorbing and relaxing the absorption is used. A polyimide resin such as Kapton (trade name) is used as the second insulating resin layer (5). Such a polyimide resin has a ductility property of about 80 to 85%, and can sufficiently absorb and reduce stress caused by a heat cycle.
【００１４】ところで、パワー半導体素子（６）が搭載
される第１の絶縁樹脂層（２）は基板（１）の全面に貼
着される。このとき、第１の絶縁樹脂層（２）のパワー
半導体素子（６）の固着領域には、あらかじめ銅箔が一
体化されている。そして、その銅箔をエッチングしてパ
ワー半導体素子（６）が固着される固着パッド（３）と
その固着パッド（３）から延在されたパワー用導電路
（図示しない）が形成される。The first insulating resin layer (2) on which the power semiconductor element (6) is mounted is attached to the entire surface of the substrate (1). At this time, a copper foil is integrated in advance in the fixed region of the first insulating resin layer (2) to the power semiconductor element (6). Then, the copper foil is etched to form a fixing pad (3) to which the power semiconductor element (6) is fixed and a power conductive path (not shown) extending from the fixing pad (3).
【００１５】パワー半導体素子（６）の固着領域以外の
第１の絶縁樹脂層（２）上に接着剤層（６Ａ）を介して
上記した第２の絶縁樹脂層（５）が貼着される。第２の
絶縁樹脂層（５）上にはあらかじめ接着剤層（６Ｂ）を
介して銅箔が一体化され、上述したパワー半導体素子
（６）の固着領域を囲むような孔（７）が設けられてい
る。この孔（７）により先に形成した固着パッド（３）
及びパワー用導電路が表面に露出されることになる。第
１の絶縁樹脂層（２）上に第２の絶縁樹脂層（５）を貼
着した後、第２の絶縁樹脂層（５）上の銅箔をエッチン
グして所望形状の導電路（３）が形成される。このと
き、第１の絶縁樹脂層（２）の露出部分、即ち、パワー
半導体固着パッド（３）及びパワー用導電路上には保護
用のレジストインクが塗布されているために何んら悪影
響は発生しない。The above-mentioned second insulating resin layer (5) is adhered on the first insulating resin layer (2) other than the fixing region of the power semiconductor element (6) via an adhesive layer (6A). . A copper foil is integrated on the second insulating resin layer (5) via an adhesive layer (6B) in advance, and a hole (7) is provided so as to surround the fixing region of the power semiconductor element (6). Have been. The fixing pad (3) previously formed by the hole (7)
In addition, the power conductive path is exposed on the surface. After adhering the second insulating resin layer (5) on the first insulating resin layer (2), the copper foil on the second insulating resin layer (5) is etched to form a conductive path (3) having a desired shape. ) Is formed. At this time, since the protective resist ink is applied to the exposed portion of the first insulating resin layer (2), that is, the power semiconductor fixing pad (3) and the power conductive path, no adverse effect occurs. do not do.
【００１６】基板（１）上に第１の絶縁樹脂層（２）及
び第２の絶縁樹脂層（５）を貼着し、夫々の樹脂層
（２）（５）上に所定の導電路（３）（３）を形成した
後、かかる導電路（３）（３）上に所定の回路素子が搭
載される。即ち、第１の絶縁樹脂層（２）上の固着パッ
ド（３）にはろう材により固着された銅片等のヒートシ
ンク（８）を介してパワー半導体素子（６）が搭載接続
される。一方、第２の絶縁樹脂層（５）上の導電路
（３）にはチップ抵抗、チップコンデンサー等のチップ
部品（４）及び図示はされないがその他の小信号系の半
導体素子が半田等のろう材により固着搭載されている。A first insulating resin layer (2) and a second insulating resin layer (5) are adhered on a substrate (1), and a predetermined conductive path (5) is formed on each of the resin layers (2) and (5). 3) After forming (3), predetermined circuit elements are mounted on the conductive paths (3) and (3). That is, the power semiconductor element (6) is mounted and connected to the fixing pad (3) on the first insulating resin layer (2) via a heat sink (8) such as a copper piece fixed by a brazing material. On the other hand, on the conductive path (3) on the second insulating resin layer (5), chip components (4) such as a chip resistor and a chip capacitor and other small-signal semiconductor elements (not shown) such as solder are used. It is fixedly mounted by a material.
【００１７】そして、パワー半導体素子（６）は第２の
絶縁樹脂層（５）の孔（７）の周端部に延在された導電
路（３）とワイヤ線（９）により接続され、パワー半導
体素子（６）と他の回路素子（４）とが相互に電気接続
されることになる。このとき、導電路（３）上にはワイ
ヤボンディングを容易にするためにＮｉメッキ（１０）
処理が施されている。The power semiconductor element (6) is connected to a conductive path (3) extending at the peripheral end of the hole (7) of the second insulating resin layer (5) by a wire (9). The power semiconductor element (6) and the other circuit element (4) are electrically connected to each other. At this time, Ni plating (10) is applied on the conductive path (3) to facilitate wire bonding.
Processing has been applied.
【００１８】本発明の構造に依れば、基板（１）上に上
述したように低熱抵抗樹脂層の第１の絶縁樹脂層（２）
と延性特性を有する第２の絶縁樹脂層（５）とを備えて
いるために発熱を有するパワー半導体素子の熱量を十分
に放散できると共に厳しい温度サイクル、例えば−５０
〜＋１５０℃範囲であってもαの差によるチップ抵抗、
チップコンデンサー等のチップ部品（４）の半田接合部
に生ずるストレスは第２の絶縁樹脂層（５）によって吸
収されるため、従来の如き、半田接合部のクラック発生
を著しく抑制することができる。According to the structure of the present invention, the first insulating resin layer (2) of the low heat resistance resin layer is formed on the substrate (1) as described above.
And the second insulating resin layer (5) having ductility characteristics, it is possible to sufficiently dissipate the heat of the power semiconductor element having heat generation and to perform a severe temperature cycle, for example, -50.
Chip resistance due to the difference in α even in the range of
Since the stress generated in the solder joint of the chip component (4) such as a chip capacitor is absorbed by the second insulating resin layer (5), it is possible to significantly suppress the occurrence of cracks in the solder joint as in the related art.
【００１９】それでは、本発明構造を用いると何故チッ
プコンデンサー、チップ抵抗等のチップ部品（４）の半
田接合部にクラックが生じにくくなることを図２を示し
て説明する。チップ部品（４）を固着した基板（１）を
約１５０℃の高温状態に放置すると基板（１）のαが２
３×１０-6／℃と大きいために基板（１）には矢印に示
す大きな応力が生じる。そして、第１の絶縁樹脂層
（２）も所定含有量のフィラーが混入されているために
αが約２３×１０-6／℃と大きくなるため基板（１）と
同様に大きな応力が生じる。この第１の絶縁樹脂層
（２）に生じる応力は、膜厚が約数十μと薄いため実質
的には基板（１）の応力がそのまま第１の絶縁樹脂層
（２）に伝達される。しかし、チップ部品（４）は延性
特性を有する第２の絶縁樹脂層（５）上に搭載されてい
るため、基板（１）で生じた大きな応力は第２の絶縁樹
脂層（５）内で厚み方向に従って矢印の如く吸収緩和さ
れ、半田接合部（１１）には基板（１）で生じた大きな
応力が加わらないことになる。このとき、第２の絶縁樹
脂層（５）の膜厚が約１０μ以下だと基板（１）で生じ
た応力を有効に緩和することができないために、第２の
絶縁樹脂層（５）の膜厚を約１０μ以上に設定すると十
分に基板（１）で発生した応力を緩和することができ
る。以上に述べたように基板（１）で発生した応力は第
２の絶縁樹脂層（５）内で緩和されるために、半田接合
部（１１）の半田成分の微結晶状態が保持され半田接合
部とコンデンサー等のチップ部品（４）の界面にクラッ
クが発生しないものである。The reason why cracks are less likely to occur in the solder joints of chip components (4) such as chip capacitors and chip resistors when the structure of the present invention is used will be described with reference to FIG. When the substrate (1) to which the chip component (4) is fixed is left at a high temperature of about 150 ° C., the α of the substrate (1) becomes 2
Since it is as large as 3 × 10 −6 / ° C., a large stress shown by an arrow is generated in the substrate (1). Since the first insulating resin layer (2) also contains a predetermined amount of filler, α increases to about 23 × 10 −6 / ° C., so that a large stress is generated as in the case of the substrate (1). Since the stress generated in the first insulating resin layer (2) is as thin as about several tens μ, the stress of the substrate (1) is substantially transmitted to the first insulating resin layer (2) as it is. . However, since the chip component (4) is mounted on the second insulating resin layer (5) having ductility characteristics, a large stress generated in the substrate (1) is generated in the second insulating resin layer (5). Absorption is alleviated as indicated by the arrow in the thickness direction, so that a large stress generated in the substrate (1) is not applied to the solder joint (11). At this time, if the thickness of the second insulating resin layer (5) is about 10 μm or less, the stress generated in the substrate (1) cannot be effectively relaxed. When the film thickness is set to about 10 μ or more, the stress generated in the substrate (1) can be sufficiently reduced. As described above, since the stress generated in the substrate (1) is relieved in the second insulating resin layer (5), the microcrystalline state of the solder component in the solder joint (11) is maintained and the solder joint is maintained. Cracks do not occur at the interface between the part and the chip component (4) such as a capacitor.
【００２０】一方、図３は本発明の構造（Ａ）と従来の
構造（Ｂ）上にチップコンデンサー（４）を搭載したと
きの温度サイクル試験での半田接合部へのクラック発生
不良率を示した特性図である。尚、温度サイクル条件は
−４０℃（３０分）〜＋１２５℃（３０分）で行い、ア
ルミニウム基板上に３．２×１．６ｍｍのチップコンデ
ンサーを搭載した。図から明らかな如く、従来の（Ｂ）
では６７０サイクルで不良が発生し始め、１０００サイ
クルでは試験サンプル数８個中全てのサンプルで半田ク
ラックによる接続不良が発生した。それに対して、本発
明の（Ａ）では１５００サイクルにおいても半田接合部
のクラックの発生が全くないことが確認された。On the other hand, FIG. 3 shows a failure rate of crack generation at a solder joint in a temperature cycle test when a chip capacitor (4) is mounted on the structure (A) of the present invention and the conventional structure (B). FIG. The temperature cycle was performed at -40 ° C. (30 minutes) to + 125 ° C. (30 minutes), and a 3.2 × 1.6 mm chip capacitor was mounted on an aluminum substrate. As is clear from the figure, the conventional (B)
In 670 cycles, failure began to occur, and in 1000 cycles, connection failure due to solder cracks occurred in all of the eight test samples. On the other hand, in the case of (A) of the present invention, it was confirmed that no crack was generated in the solder joint even at 1500 cycles.
【００２１】[0021]
【発明の効果】以上に詳述した如く、本発明に依れば、
厳い条件下の温度サイクルにおいても、チップコンデン
サー、チップ抵抗等のチップ部品の半田接合部に生じて
いたクラック発生を略完全に防止することができる。そ
の結果、パワー半導体素子の熱放散性に優れかつ極めて
厳い温度サイクル条件下に適合した高信頼性の大出力用
の混成集積回路を実現することができる。As described in detail above, according to the present invention,
Even under a temperature cycle under severe conditions, it is possible to almost completely prevent cracks occurring at the solder joints of chip components such as chip capacitors and chip resistors. As a result, it is possible to realize a high-reliability, high-output hybrid integrated circuit which is excellent in heat dissipation of the power semiconductor element and adapted under extremely severe temperature cycle conditions.
【図１】図１は本発明の実施例を示す要部拡大断面図で
ある。FIG. 1 is an enlarged sectional view of a main part showing an embodiment of the present invention.
【図２】図２は本発明の実施例の半田接合部における応
力を説明する図である。FIG. 2 is a diagram for explaining stress at a solder joint according to an embodiment of the present invention.
【図３】図３は温度サイクル試験における半田接合部の
クラック発生不良率を示す特性図である。FIG. 3 is a characteristic diagram showing a crack generation failure rate of a solder joint in a temperature cycle test.
【図４】図４は従来の混成集積回路を示す断面図であ
る。FIG. 4 is a sectional view showing a conventional hybrid integrated circuit.
【図５】図５は従来の半田接合部における応力を説明す
る図である。FIG. 5 is a view for explaining stress at a conventional solder joint.
（１） 金属基板 （２） 第１の絶縁樹脂層 （３） 導電路 （４） チップ部品 （５） 第２の絶縁樹脂層 （６） パワー半導体素子 (1) Metal substrate (2) First insulating resin layer (3) Conductive path (4) Chip component (5) Second insulating resin layer (6) Power semiconductor element
Claims (4)
れた導電路上にパワー半導体素子及び他の回路素子が固
着搭載された混成集積回路において、 前記パワー半導体素子は所望重量比のフィラーが混入さ
れた低熱抵抗樹脂層上に搭載され、前記他の回路素子は
延性特性を有した絶縁樹脂層上に搭載されたことを特徴
とする混成集積回路。1. A hybrid integrated circuit having a power semiconductor element and another circuit element fixedly mounted on a conductive path formed on a metal substrate via an insulating resin layer, wherein the power semiconductor element contains a filler having a desired weight ratio. A hybrid integrated circuit mounted on a mixed low heat resistance resin layer, wherein the other circuit element is mounted on an insulating resin layer having ductility characteristics.
低熱抵抗樹脂層上に設けたことを特徴とする請求項１記
載の混成集積回路。2. The hybrid integrated circuit according to claim 1, wherein said insulating resin layer having ductility is provided on said low heat resistance resin layer.
るいはチップコンデンサーを用いたことを特徴とする請
求項１記載の混成集積回路。3. The hybrid integrated circuit according to claim 1, wherein a chip resistor or a chip capacitor is used as said another circuit element.
ポリイミド樹脂を用いたことを特徴とする請求項１記載
の混成集積回路。4. The hybrid integrated circuit according to claim 1, wherein a polyimide resin is used as said insulating resin layer having ductility characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188861A JP2919651B2 (en) | 1991-07-29 | 1991-07-29 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188861A JP2919651B2 (en) | 1991-07-29 | 1991-07-29 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0537105A JPH0537105A (en) | 1993-02-12 |
| JP2919651B2 true JP2919651B2 (en) | 1999-07-12 |
Family
ID=16231149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3188861A Expired - Fee Related JP2919651B2 (en) | 1991-07-29 | 1991-07-29 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2919651B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112005000748T5 (en) * | 2004-04-06 | 2007-05-16 | Honda Motor Co Ltd | Semiconductor element mounting substrate, semiconductor module and electric vehicle |
| KR101109359B1 (en) * | 2010-06-14 | 2012-01-31 | 삼성전기주식회사 | Heat-radiating substrate and manufacturing method thereof |
| JPWO2013132569A1 (en) * | 2012-03-05 | 2015-07-30 | 三菱電機株式会社 | Semiconductor device |
| DE112012005984T5 (en) * | 2012-03-05 | 2014-12-04 | Mitsubishi Electric Corporation | Semiconductor device |
| JP5987719B2 (en) * | 2013-02-13 | 2016-09-07 | 三菱電機株式会社 | Semiconductor device |
-
1991
- 1991-07-29 JP JP3188861A patent/JP2919651B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0537105A (en) | 1993-02-12 |
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