JPS6174043A - Memory control system - Google Patents

Abstract

PURPOSE:To shorten a reading time of a memory together with an error correction by displaying a failure bit position of a memory means comprising a memory using an optional bit for every bank and using a redundant bit in place of the failure bit. CONSTITUTION:Memory circuits 12-1-12-N connected to an error detection and correction circuit 11 through a data signal line 101 and a memory circuit 13 connected to the circuit 11 through the data signal line 101 and a driver/ receiver 14 are provided in a memory bank 1, and N of the circuits 12-1-12-N is made equal to the number of a data bit to correspond to a redundant bit. The circuits 12-1-12-N, 13 are respectively chip selected by signal lines 203, 202, and made effective and a receiver 14 is effective when any one of the line 203 makes any one of the circuits 12-1-12-N invalid and the circuit 13 is connected to the line 101 through the effective receiver 14.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control method for a storage device used for signal processing.

(Conventional technology) Conventional 1. This type of storage control system cannot use redundant bits that can replace faulty bits in addition to error detection and correction codes.

(Until the invention is solved) For this reason, 2-bit error correction requires a large number of redundant bits, and a memory read with error correction requires more redundant bits than a fault-free memory read. The disadvantage was that it required a lot of time.

An object of the present invention is to eliminate the above-mentioned drawbacks by using redundant bits that can be substituted for faulty bits in addition to error detection and correction codes, and to enable 2-bit error correction with a small number of redundant bits, thereby reducing 1-bit error faults. It is an object of the present invention to provide a storage control system configured so that reading of a bank having a failure can be executed in the same time as a bank without a fault.

(Means for Solving the Problems) The storage control system according to the present invention uses redundant bits that can replace faulty bits in addition to error burst correction codes, and uses memory means consisting of arbitrary bits for each bank. Redundant bit selection means for using one storage means consisting of redundant bits instead, and error detection for performing error detection and correction on 24 means consisting of memory using arbitrary bits. correction means, and status display means for displaying a failure state of the storage means comprising a memory for each bank;
Each bank consists of a memory, ii'! This is realized by comprising a faulty pit device display means for displaying the faulty bit position 14 of the storage means, and a faulty pit replacement means for using a redundant flyer in place of the faulty bit displayed by the faulty bit position display means. This is what I did.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment for realizing a storage control method according to the present invention.

In FIG. 1, 1 is a memory bank, 11 is an error detection and correction circuit, 12-1 to 1z-N, 13 are storage circuits, and 14 is a driver/receiver. Memory bank 1 is connected to error detection and correction circuit 11 via data signal line 101.
The memory circuit 13 includes memory circuits 12-1 to 12-N connected to the error detection and correction circuit 11 via the data signal line 101 and the driver/receiver 14.

Memory circuits 12-1 to 12-N included in memory bank 1
The number N is equal to the number of data bits, and the memory circuit 13 corresponds to redundant bits. The memory bank 1 is connected to an error detection and correction circuit 11 through a data signal line 101, and the error detection and correction circuit 11 is connected to a data bus signal line 102.

FIG. 2 is a block diagram of a control circuit provided corresponding to all memory banks 1. Control circuit is register 2
3, a decoder 24 connected to the output of the register 23, and a first and second 7-lag 7-lip flop 21.22.
and AND gates 25 to 2B. The signal line 201 is an AND output of the output of the first flag flip-flop 21 and the signal on the signal line 204, and is ORed with the signal line 201 of another in-bank memory control circuit and connected to the error injection correction circuit 11. has been done. The signal on signal line 202 is the output of second flag flip-flop 22 and is connected to storage circuit 13. The signal on the signal line 203 is an AND output of the output signal on the output signal line 202 of the second flag flip-flop 22 and the output of the decoder 24.
and driver/receiver 14.

Next, the operation of the Honju Senretsu will be explained in detail.

2 in FIG. 1, Kiichikura circuits 12-1 to 12-N.

13 is an IC memory of 64 words (for example, 1 pin), and the chip 7 (selected and enabled by line 7 line 202 or signal line 203) is connected to the driver/receiver 1.
4, one of the signal lines 203 is connected to the memory circuit 12-1
~12-N is effective when controlling the signal line 202.
When the memory circuit 13 enabled by b is connected to the data signal line 101 through all the enabled drivers/receivers 14, the function of one of the memory circuits b can be substituted by the memory circuit 13.

In FIG. 2, the register 23 stores the fault data bit position of the corresponding memory bank, and is decoded by the decoder 24. Second flag flip-flop 2
Second, it is for displaying that a faulty bit has occurred. Therefore, when i harm is indicated by the flag flip 70 knob 22 of $, 2, and the state of the signal line 203 corresponding to the data bit indicated by the register 23 becomes 1, the storage circuit 12 connected to the signal line 203 - 1 becomes invalid, and the memory circuit 13 becomes valid instead. The first 7-bit flip 70 tab 21 is for all error correction instructions. An in-bank memory control circuit as shown in FIG. 2 is provided for each bank, and the signal on the signal line 204 indicating access and the output of the first flag flip-flop 21 are ANDed. Therefore, only the first output data from the memory bank for which error correction has been instructed is corrected by the error detection and correction circuit 11 that responds to the signal on the signal line 201, and then output. That is, it is assumed that a failure is detected by the error detection and correction circuit 11 when the bank is accessed.

At this time, if the fault is a 1-bit error that can be corrected, a nuisance is displayed on the second flag flip-flop 22,
By storing the faulty pit position and repair information obtained by the error detection and correction circuit 11 in the register 23, the storage circuit 13 performs the function on behalf of the user from the next access.

In the above operation, if the fault is a 2-pit error that cannot be corrected, the first and second flags are set in the flip-flops 21 and 22iL, and each time a value from O to the number of data bits is stored in the register 23. The address where the failure occurred is read and stored. When the data stored in the register 23 is incremented by 1, the data bit for which the memory circuit 13 acts matches one of the two pits that caused the fault, so the detected fault is a 1-bit error that can be corrected. Changes to That is, by holding the contents of the register 23 at this time and using the 1-bit error correction function of the error detection circuit 11, 2-pit error correction is executed.

(Effects of the Invention) As explained above, the present invention determines the number of redundant bits necessary for 2-bit error correction by adding only 1 bit to the number of redundant bits for 1-bit error correction,
Furthermore, by eliminating the need for i-correction, which requires more time, in the event of a single-bit error failure, highly reliable memory can be realized economically and without significantly increasing access time. There is an effect that says it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a practical example for implementing the storage control method according to the present invention. FIG. 2 is a block diagram showing an embodiment of an in-bank memory control circuit corresponding to the memory bank shown in FIG. 1...Memory bank 11...Error detection and correction circuits 12-1 to 12-N, 13...Storage circuit 14...Driver/receiver 21.22...Flip-flop 23...Register 24. ...Decoder patent applicant Nippon Ichiki Co., Ltd. agent Patent attorney Inoro 11 Humiliation 2
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Claims (1)

[Claims] redundant bit selection means for using a storage means made up of redundant bits instead of a storage means made up of arbitrary bits for each bank; and error detection and correction applied to the storage means made up of a memory using said arbitrary bits. error detection and correction means for displaying a failure state of the storage means comprising the memory for each bank; and status display means for displaying a faulty bit position of the storage means comprising the memory for each bank. 1. A storage control system comprising a faulty bit position display means and an alternative means for using the redundant bit in place of the faulty bit displayed by the faulty bit position display means.