JPS6171652A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6171652A
JPS6171652A JP59192597A JP19259784A JPS6171652A JP S6171652 A JPS6171652 A JP S6171652A JP 59192597 A JP59192597 A JP 59192597A JP 19259784 A JP19259784 A JP 19259784A JP S6171652 A JPS6171652 A JP S6171652A
Authority
JP
Japan
Prior art keywords
lead
bent
resin
sealed
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59192597A
Other languages
Japanese (ja)
Inventor
Yutaka Okuaki
奥秋　裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59192597A priority Critical patent/JPS6171652A/en
Publication of JPS6171652A publication Critical patent/JPS6171652A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of cracks by a method wherein the chip part and part of the lead frame are sealed with sealing resin; next, the bent part of the lead frame is buried and sealed so that this part of trapezoidal or reverse parabolic form is embedded in inside and exposed in outside. CONSTITUTION:The lead frame 1 with a semiconductor chip 4 is resin-sealed so that the semiconductor chip 4, metallic fine wires 5, outer lead connections of the wires 5, etc. are protected by surrounding with a sealing resin 30. Thereafter, the bent part 12a is formed by bending downward the outer leads 12; further, its tip is trapezoidally bent into the bent part 32, and the bent parts 12a and 32 are resin-sealed with a sealing resin 31. In this case, the bent part 12a is surrounded with the sealing resin 31, and the bent part 32 is half- embedded. This manner allows no projection of outer leads out of the resin- sealed part and can prevent the generation of lead bending and cracks caused by lead bending.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は、小型多ピンのＰＬＣＣ（プラスチックのリ
ード付きキャップキャリヤ）の実装に際し、リードの曲
りやクラックの発生を防止できるようにした半導体装置
に関する。[Detailed Description of the Invention] (Industrial Application Field) This invention is a semiconductor device that can prevent lead bending and cracking when mounting a small multi-pin PLCC (plastic leaded cap carrier). Regarding.

（従来の技術） 樹脂封止半導体装置（以下１Ｇという）は、プレスまた
はエツチング加工された、リードフレームと称されろ素
子搭載部に半導体素子を人ｕ　−Ｓｉ共晶または樹脂ペ
ーストによってｆ／ＸＷＩ、、半導体素子外部導出端子
電極部（バット部）と外部導出リードとを金属細線によ
って導通接続させ、半導体素子と金属細線とを接続した
リード部分をトランスファーモールディング方式によっ
て４１１１１　封止することによって形成される。(Prior art) A resin-sealed semiconductor device (hereinafter referred to as 1G) is manufactured by attaching a semiconductor element to an element mounting part called a lead frame, which is pressed or etched, using f/XWI eutectic or resin paste. It is formed by electrically connecting the semiconductor element external lead terminal electrode part (butt part) and the external lead lead with a thin metal wire, and sealing the lead part connecting the semiconductor element and the metal wire using a transfer molding method. Ru.

このようなＩＣはセラミック半導体装置に比較して原材
料的に、また製造コスト的にもはるかに、安価に！！造
できるので、近年セラミック半導体装置の樹脂封止型半
導体装置への転換がなされている。Such ICs are much cheaper in terms of raw materials and manufacturing costs than ceramic semiconductor devices! ! In recent years, there has been a shift from ceramic semiconductor devices to resin-sealed semiconductor devices.

また、パッケージの小形化、薄形化も技術的、また市場
の要求する方向である。これらの方向にそった種々の樹
脂封止化され、小形化されたチャプキャリャ（日経エレ
クトロニクス、マイクロデバイス１９８４．６．１１．
１４８Ｐ〜１５９Ｐ、　　　、１８７Ｐ〜２０５Ｐなど
に示されている）が製造されている。Furthermore, smaller and thinner packages are also a direction demanded by technology and the market. Various resin-sealed and miniaturized chap carriers along these directions (Nikkei Electronics, Microdevice 1984.6.11.
148P to 159P, , 187P to 205P, etc.) are manufactured.

セラミックタイプのチップキャリヤは外部のリードのな
いリードレスチップキャリヤと称され、樹脂封止された
チップキャリヤは外部のリードを短くしたリープイツト
チップキャリヤと　称され、これら両者ともに小形化、
薄形化され、プリント基板などへ従来のディップ型のス
ルーホールなどを利用した装着ではなく、基板の平面に
、ハンダ付けによって装着されている。Ceramic type chip carriers are called leadless chip carriers that do not have external leads, and resin-sealed chip carriers are called leapt chip carriers that have short external leads.
It is thinner and is attached to a printed circuit board by soldering to the flat surface of the board, rather than using conventional dip-type through holes.

ここで、第２図、第３図によって従来のチップキャリヤ
を説明する。この第２図、第３図は、従来技術によって
製造された一般的なＰＬＣＣの実装構造である。まず、
第２図に示すように、リードフレーム１にＡｕ　−５ｉ
　または樹脂ペースト２などによってアイランド部３に
載置された半導体チンプ４を金属細線５によって外部導
出リード１２と半導体チップ４の電極部とを導通させる
。Here, a conventional chip carrier will be explained with reference to FIGS. 2 and 3. These FIGS. 2 and 3 show the mounting structure of a general PLCC manufactured by the conventional technology. first,
As shown in FIG. 2, the lead frame 1 is made of Au-5i.
Alternatively, the semiconductor chip 4 placed on the island portion 3 with resin paste 2 or the like is electrically connected to the external lead 12 and the electrode portion of the semiconductor chip 4 through the thin metal wire 5.

その後、第２図に示すように、トランスファーモールデ
ィング方式によって第１の封止樹脂２０（使用されろ樹
脂はエポキシ樹脂が主に使われろ）によって封止し、外
部導出リード１２をｒＪＪ字形状に折り曲げ加工される
が、第１のリード折り曲げ部２１は、はぼ直角近くにプ
レス加工によって折り曲げられる。また、第２のリード
折り曲げ先端部２２もプレス加工によって折り曲げられ
ろ。Thereafter, as shown in FIG. 2, the external leads 12 are sealed with a first sealing resin 20 (epoxy resin is mainly used) by a transfer molding method, and the external leads 12 are bent into an rJJ shape. The first lead bent portion 21 is bent almost at a right angle by press working. Further, the second lead bending tip 22 is also bent by press working.

（発明が解決しようとする問題点） しかしながら、第１のリード折り曲げ部２１は折り曲げ
による応力によってクラックなどが発生し、「Ｊ」字状
に折り曲げられたリード１２と第１の封止４ｉｆｌｌ１
２ｏとのすきまが接近しているので、リード１２のハン
ダディップ処理工程でリード１２の酸化皮膜除去などの
酸処理液の洗浄作業が困難であった。(Problems to be Solved by the Invention) However, cracks occur in the first lead bent portion 21 due to stress caused by bending, and the lead 12 bent in a “J” shape and the first seal 4ifll1
Since the gap between the lead 12 and the lead 2o is close to each other, it is difficult to clean the lead 12 with an acid treatment liquid such as removing an oxide film in the solder dipping process of the lead 12.

また、酸処理液などによって第１のリード折り曲げ部２
１が応力腐食（応力が加わったところがくさび状に腐食
する）などの腐食によってリード強度の劣化などの不都
合が生じていた。In addition, the first lead bent portion 2 may be
No. 1 had problems such as deterioration of lead strength due to corrosion such as stress corrosion (wedge-shaped corrosion where stress is applied).

さらに、３字状に折り曲げられたリードの内側はハンダ
ディップ処理時にハンダ未着、フラックスの残渣などが
残り、洗浄作業が困難であった。Furthermore, during the solder dipping process, unsoldered and flux residues remained on the inside of the three-shaped lead, making cleaning difficult.

このように、従来のＰＬＣＣは、リード強度の劣化、わ
ずられしいリード折り曲げ加工、「Ｊ」字状リードの内
側のハンダ処理、洗浄が困難であろなどの不都合がある
とともに、４！１１１Ｎ成形後折り曲げ加工するので、
作業が非常にむずかしく曲線状に折り曲げるので曲げ加
工性がよ（ない。As described above, conventional PLCCs have disadvantages such as deterioration in lead strength, troublesome lead bending, soldering inside the "J" shaped leads, and difficulty in cleaning. Since the bending process is done afterward,
The work is very difficult and bending is difficult, as it has to be bent into a curved shape.

この発明は、前記従来技術が持っていた問題点のうら、
「Ｊ」字状に折り曲げ加工または折り曲げ部分のクラッ
ク、「Ｊ」字状の折り曲げリードの内側のハンダ処理、
洗浄などの問題点を解決した半導体装置を提供すること
を目的とする。This invention solves the problems that the prior art had,
Bending the lead into a “J” shape or cracking the bent part, soldering the inside of the “J” bent lead,
The purpose is to provide a semiconductor device that solves problems such as cleaning.

ｆ発明が解決ずろための手段） この発明は、ＰＬＣＣ装置において、半導体チップ部お
よびそれと金属細線を介して接続したリードフレームの
１部のみを包囲保護する第１の封止樹脂と、この第１の
封Ｌｌ：位（脂で封止された部分のツー′１−フレーム
を所定の角度で折り曲げた第１の折り曲げ部を埋設する
とともに台形あるいは逆・　　放物佇状に折り曲げた第
２の折り曲げ部の内側部分を埋め込み、その外側部分ｉ
ｅ露出するように封止する第２の封止樹脂とを設けたも
のである。(Means for Solving the Problems of the Invention) In a PLCC device, the present invention provides a first sealing resin that surrounds and protects only a semiconductor chip portion and a part of a lead frame connected thereto via a thin metal wire; Sealing Ll: Place (2'1 of the part sealed with fat) bury the first bent part by bending the frame at a predetermined angle, and the second bending by bending it into a trapezoid or inverted/parabolic shape. embedding the inner part of the part and its outer part i
(e) and a second sealing resin that is sealed so as to be exposed.

（作　用） この発明によれば、以上のように半導体装置を構成した
ので、樹脂封止を２回に分けて第１の封止樹脂で半導体
チップおよびリードフレームの一部のみを封止した後、
リードフレームを第１．＠２の折り曲げ部を形成し、第
１の折り曲げ部は全体を第２の封止樹脂で埋め込み、第
２の折り曲げ部は内側のみを第２の封止樹脂内に埋め込
み、第２の折り曲げ部の外側は第２の封止樹脂の外部に
露出させることにより、前記問題点を解決できろ。(Function) According to the present invention, since the semiconductor device is configured as described above, the resin sealing is divided into two steps and only a part of the semiconductor chip and the lead frame are sealed with the first sealing resin. rear,
Place the lead frame first. @2 bent portions are formed, the first bent portion is entirely embedded in the second sealing resin, only the inside of the second bent portion is embedded in the second sealing resin, and the second bent portion is filled with the second bent portion. The above problem can be solved by exposing the outside of the second sealing resin to the outside of the second sealing resin.

（実施例） 以下、この発明の半導体装置の実施例について図面に基
づき説明する。第１図はその一実施例の構成を示す断面
図である。この第１図において、第２図および第３図に
示したリードフレームｌに入ｕ　−Ｓｉ　または樹脂ペ
ースト２などによってアイランド３に半導体チップ４を
搭載し、半導体チップ４のＴｉ極とリードフレーム１を
金属細線５て接続しｔ−リードフレームを用いてこの発
明を実施しており、したがって、この第１図において、
第２図および第３図と同一部分に（よ同一符号を付する
にとどめろ。(Embodiments) Hereinafter, embodiments of the semiconductor device of the present invention will be described based on the drawings. FIG. 1 is a sectional view showing the configuration of one embodiment. In this FIG. 1, a semiconductor chip 4 is mounted on an island 3 using U-Si or resin paste 2 into the lead frame l shown in FIGS. 2 and 3, and the Ti pole of the semiconductor chip 4 and the lead frame 1 This invention is implemented using a T-lead frame in which the metal wires 5 are used to connect the
The same parts as in FIGS. 2 and 3 are given the same reference numerals.

第１図において、半導体チップ４を載置したり−＋；フ
レーム１を第１の封止樹脂３０によって半導体チップ４
、金属細線５、金属細線５の外部導出接続部などを包囲
保護するように樹脂封止する。In FIG. 1, the semiconductor chip 4 is placed on the frame 1 by the first sealing resin 30.
, the thin metal wire 5, the external lead-out connection portion of the thin metal wire 5, etc. are sealed with resin so as to surround and protect them.

その後、外部導出リード１２を下方向に折り曲げ加工し
て第１の折り曲げ部１２ａを形成し、さらに、その先端
を台形状に折り曲げて第２の折り曲げ部３２を形成し、
第２の封止樹脂３１によって第１の折り曲げ部１２ａ、
第２の折り曲げ部３２を四脂封ＩＦする。After that, the external lead-out lead 12 is bent downward to form a first bent part 12a, and the tip thereof is further bent into a trapezoid shape to form a second bent part 32,
The first bent portion 12a is formed by the second sealing resin 31,
The second bent portion 32 is sealed IF.

この場合、第１の折り曲げ部１２ａを第２の封止樹脂３
１て包囲し、第２の折り曲げ部３２は第１図より明らか
なように半分埋め込むような形にする。ひれ（よ成型金
型にセントして射出成形することにより、外部導出リー
ド１２の第２の折り曲げ部３２は第２の封止樹脂に密着
してしつかり固定されろ。In this case, the first bent portion 12a is connected to the second sealing resin 3.
1, and the second bent portion 32 is shaped so as to be half-embedded, as is clear from FIG. By inserting the fin into a mold and performing injection molding, the second bent portion 32 of the external lead 12 is tightly fixed to the second sealing resin.

このように、樹脂封止工程を２回に分割し、外部導出リ
ード１２を樹脂封止することによって、封止樹脂から突
き出たリードを急角度で折り曲げ加工することによって
発生した、リードのクラックなどがなく、リードの第２
の折り曲げ部３２が樹脂封止されているので、リード曲
がりなどもなく、リード折り曲げ工程が容易である。In this way, by dividing the resin sealing process into two steps and sealing the external leads 12 with resin, cracks in the leads that occur due to bending the leads protruding from the sealing resin at a steep angle can be avoided. There is no second lead
Since the bending portion 32 is sealed with resin, there is no lead bending, and the lead bending process is easy.

また、第２の封止樹脂３１から突出した第２の折り曲げ
部３２のリード表面３２ａには第２の封止樹脂３１の充
填のときにモールドフラソノユといわれる極薄い樹脂皮
膜が形成されるが、液体ホーニングといわれる水溶液中
に研友剤を含ませて（混合して）、加圧して吹き付ける
方法によって容易に除去できろ。Furthermore, an extremely thin resin film called a mold flask is formed on the lead surface 32a of the second bent portion 32 protruding from the second sealing resin 31 when the second sealing resin 31 is filled. It can be easily removed by a method called liquid honing, in which a polishing agent is soaked (mixed) in an aqueous solution and sprayed under pressure.

なお、第１の封止樹脂３０によろ封止後、’Ｊ　−ド折
り曲げ前にリード表面をハング処理をしておくと、第２
の樹脂封止後リード酸処理がなく、リードと樹脂との界
面から処理薬品などの浸入が防止できる。Note that after sealing with the first sealing resin 30 and before bending the lead, it is possible to
There is no lead acid treatment after resin sealing, and processing chemicals can be prevented from entering through the interface between the lead and the resin.

第１の封止Ｄ（脂３０と第２の封止樹脂３１の界面３３
ば、平面接触だと密着強度がないので、歯車のかみ合う
状態で接触した方が密着強度が増加する。First sealing D (interface 33 between fat 30 and second sealing resin 31
For example, since there is no adhesion strength with flat contact, the adhesion strength increases when the gears are in meshed contact.

なｊＢ、外部リード１２の第２の折り曲げ部３２の形状
は第１図のほかに、逆放物線状にすることによって応力
をより減少できる。In addition to the shape shown in FIG. 1, the stress can be further reduced by making the second bent portion 32 of the external lead 12 into an inverted parabolic shape.

（発明の効果） ↓上玉詳細に説明したようにこの発明によれば、樹脂封
止を２回に分割して外部導出リードの折り曲げ加工後、
折り曲げ部ｔｅ樹脂封止ずろようにしｔ二ので、従来の
ようにリードを５字状に折り曲げたことによる直角に近
い折り曲げ部分があったのに対して、この発明は、樹脂
封止部から外部導出リードが突き出さなくなり、リード
曲がりなどもなく、また、リード折り曲げによるクラッ
クなどもなくなるという利点がある。(Effects of the invention) ↓Top ball As explained in detail, according to this invention, after dividing the resin sealing into two parts and bending the external leads,
Since the bent part is resin-sealed and the lead is bent at a right angle, unlike the conventional case where the lead is bent into a 5-shape, there is a bent part that is close to a right angle. There are advantages in that the lead-out leads do not protrude, there is no bending of the leads, and there are no cracks caused by bending the leads.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の半導体装置の一実施例の断面図、第
２図および第３図はそれぞれ従来のＰＬＣＣ装置の断面
図である。 トリードフレーム、３・アイランド部、４半導体チップ
、５　半導体細線、１２　外部Ｊ−ド、１２ａ　　・第
１の折り曲げ部、３０　第１の封ｌＪ：樹脂、３１・第
２の封止樹脂、３２　第２の折り曲げ部。FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIGS. 2 and 3 are sectional views of conventional PLCC devices, respectively. Toledo frame, 3.Island portion, 4. Semiconductor chip, 5. Semiconductor thin wire, 12. External J-de, 12a.First bent portion, 30. First sealing lJ: Resin, 31.Second sealing resin, 32. 2. Folded part.

Claims (1)

【特許請求の範囲】[Claims] アイランド部に載置された半導体チップの電極と金属細
線を介して接続されたリードフレームと、上記半導体チ
ップおよびリードフレームの一部のみを封止して包囲保
護する第１の封止樹脂と、この第１の封止樹脂で封止さ
れない部分の上記リードフレームを所定角度で折り曲げ
た第１の折り曲げを埋設するとともに台形あるいは逆放
物線に折り曲げた第２の折り曲げ部の内側部分を埋め込
みその外側部分は露出するように封止する第２の封止樹
脂とよりなる半導体装置。a lead frame connected to an electrode of a semiconductor chip placed on the island portion via a thin metal wire; a first sealing resin that seals and protects only a portion of the semiconductor chip and the lead frame; The first bent part of the lead frame that is not sealed with the first sealing resin is bent at a predetermined angle, and the inner part of the second bent part, which is bent into a trapezoid or an inverted parabola, is embedded, and the outer part thereof is embedded. A semiconductor device comprising a second sealing resin that is sealed in an exposed manner.
JP59192597A 1984-09-17 1984-09-17 Semiconductor device Pending JPS6171652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59192597A JPS6171652A (en) 1984-09-17 1984-09-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59192597A JPS6171652A (en) 1984-09-17 1984-09-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6171652A true JPS6171652A (en) 1986-04-12

Family

ID=16293911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59192597A Pending JPS6171652A (en) 1984-09-17 1984-09-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6171652A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06209227A (en) * 1994-02-01 1994-07-26 Ngk Spark Plug Co Ltd Assembling method for ladder type piezoelectric filter
EP1143465A3 (en) * 2000-04-07 2006-09-20 Nec Tokin Corporation Chip capacitor, a fabrication method for the same, and a metal mold
EP4102546A1 (en) * 2021-06-11 2022-12-14 NXP USA, Inc. An integrated circuit package and method to manufacture the integrated circuit package to reduce bond wire defects in the integrated circuit package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06209227A (en) * 1994-02-01 1994-07-26 Ngk Spark Plug Co Ltd Assembling method for ladder type piezoelectric filter
EP1143465A3 (en) * 2000-04-07 2006-09-20 Nec Tokin Corporation Chip capacitor, a fabrication method for the same, and a metal mold
EP4102546A1 (en) * 2021-06-11 2022-12-14 NXP USA, Inc. An integrated circuit package and method to manufacture the integrated circuit package to reduce bond wire defects in the integrated circuit package
US11784112B2 (en) 2021-06-11 2023-10-10 Nxp Usa, Inc. Integrated circuit package and method to manufacture the integrated circuit package to reduce bond wire defects in the integrated circuit package

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