JP2000299400A - Non-lead flat-package type semiconductor device - Google Patents

Non-lead flat-package type semiconductor device

Info

Publication number
JP2000299400A
JP2000299400A JP10668699A JP10668699A JP2000299400A JP 2000299400 A JP2000299400 A JP 2000299400A JP 10668699 A JP10668699 A JP 10668699A JP 10668699 A JP10668699 A JP 10668699A JP 2000299400 A JP2000299400 A JP 2000299400A
Authority
JP
Japan
Prior art keywords
terminals
semiconductor device
solder
terminal
sealing body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10668699A
Other languages
Japanese (ja)
Inventor
Hitoshi Maeda
仁 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10668699A priority Critical patent/JP2000299400A/en
Publication of JP2000299400A publication Critical patent/JP2000299400A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To prevent short-circuitings between projection terminals or the wiring patterns of a packaging substrate on packaging. SOLUTION: A device 20 is equipped with a number of projection terminals 22, that are used as the terminal for connecting to a packaging substrate and that project extremely short distance outward from the four sides of a nearly square-columnar shaped sealing body 12, where a semiconductor element is sealed inside with resin. The projection terminals 22 orthogonally cross each of four sides of the sealing body 12 on the same surface as the lower surface of the sealing body 12 for projecting. The projection terminals 22 do not retain resin between the projecting terminals 22, and the outer peripheral surface of the projection terminals 22 is exposed from the sealing body 12. In the projection terminal 22, a metal coating where a solder cladding property is increased and at the same time corrosion resistance is superior, is plated. When soldering junctions, since no resin exists between the projection terminals 22, creamy solder creeps into the side surface of the projection terminal, forming a solder bridge by solder to each other, preventing generation of short-circuiting phenomenon, and furthermore, increasing the strength of electrical and mechanical connections with the packaging substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ノンリード・フラ
ットパッケージ型半導体装置に関し、更に詳細には、実
装に際して、突出端子間に生じたはんだブリッジに起因
する突出端子間の短絡現象を発生させないようにしたノ
ンリード・フラットパッケージ型半導体装置に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-leaded flat package type semiconductor device, and more particularly, to preventing a short-circuit phenomenon between projecting terminals due to a solder bridge generated between projecting terminals during mounting. And a non-lead flat package type semiconductor device.

【0002】[0002]

【従来の技術】半導体装置の最近の多ピン化、微細化及
び高密度実装化の流れに伴い、平面リードピン形パッケ
ージ型半導体装置と言われるフラットパッケージ(F
P)型半導体装置のなかでも、ノンリード・フラットパ
ッケージ型半導体装置が、多用されるようになってい
る。
2. Description of the Related Art With the recent trend of increasing the number of pins, miniaturization and high-density mounting of semiconductor devices, a flat package (F) called a flat lead pin type package type semiconductor device has been developed.
Among the P) type semiconductor devices, a non-lead flat package type semiconductor device has been widely used.

【0003】ここで、図5を参照して、従来のノンリー
ド・フラットパッケージ型半導体装置の構成を説明す
る。図5(a)及び図5(b)は、それぞれ、従来のノ
ンリード・フラットパッケージ型半導体装置の平面図、
及び側面図、図6は従来のノンリード・フラットパッケ
ージ型半導体装置の斜視図、図7は図5(a)の線II−
IIでの断面図である。従来のノンリード・フラットパッ
ケージ型半導体装置10(以下、簡単に半導体装置10
と言う)は、図5(a)、(b)及び図6に示すよう
に、実装基板との接続用端子として、樹脂又はセラミッ
ク等の封止材で内部の半導体素子を封止したほぼ正四角
柱状の封止体12の4辺から外方に向けて極く短く突出
した多数の突出端子14を備えている。突出端子14
は、それぞれ、封止体14の下面と同じ面上で封止体1
4の四辺の各辺に直交して突出していて、突出端子14
と隣の突出端子14との間には、図5(a)、(b)及
び図6に示すように、封止体12と同じ樹脂15が充満
している。
Here, a configuration of a conventional non-lead flat package type semiconductor device will be described with reference to FIG. FIGS. 5A and 5B are plan views of a conventional non-lead flat package type semiconductor device, respectively.
FIG. 6 is a perspective view of a conventional non-lead flat package type semiconductor device, and FIG. 7 is a line II- of FIG.
It is sectional drawing in II. Conventional non-lead flat package type semiconductor device 10 (hereinafter simply referred to as semiconductor device 10)
5 (a), 5 (b) and FIG. 6, a substantially positive terminal in which the internal semiconductor element is sealed with a sealing material such as resin or ceramic as a terminal for connection to a mounting substrate. A large number of protruding terminals 14 protruding outward from four sides of the quadrangular prism-shaped sealing body 12 are provided. Projecting terminal 14
Respectively, on the same surface as the lower surface of the sealing body 14,
4 project perpendicularly to each of the four sides,
As shown in FIG. 5A, FIG. 5B and FIG. 6, the space between the adjacent protruding terminals 14 is filled with the same resin 15 as the sealing body 12.

【0004】また、半導体装置10は、図7に示すよう
に、封止体12内に、ダイパッド16上に接着され半導
体チップ17を有し、半導体チップ17の電極と封止体
14内に延びる突出端子14とは、ボンディングワイヤ
18によって接続されている。これにより、半導体チッ
プ17は、ボンディングワイヤ18及び突出端子14を
介して外部に接続される。
As shown in FIG. 7, the semiconductor device 10 has a semiconductor chip 17 adhered on a die pad 16 in a sealing body 12 and extends into the electrodes of the semiconductor chip 17 and the sealing body 14. The protruding terminals 14 are connected by bonding wires 18. Thus, the semiconductor chip 17 is connected to the outside via the bonding wires 18 and the protruding terminals 14.

【0005】半導体装置10を実装基板上に実装する際
には、半導体装置10は、図8に示すように、実装基板
19の配線パターン(図示せず)上のクリームはんだ1
9aを被着させたはんだランド上に突出端子14を位置
合わせし、リフロー法等により突出端子14を配線パタ
ーンにはんだ接合している。
When the semiconductor device 10 is mounted on a mounting board, as shown in FIG. 8, the cream solder 1 on the wiring pattern (not shown) of the mounting board 19 is used.
The protruding terminal 14 is positioned on the solder land on which 9a is attached, and the protruding terminal 14 is soldered to the wiring pattern by a reflow method or the like.

【0006】[0006]

【発明が解決しようとする課題】しかし、上述したよう
なノンリード・フラットパッケージ型半導体装置を実装
基板上に実装した際、半導体装置の端子間で、又は実装
基板の配線パターン間で短絡現象が発生するという問題
があった。
However, when the above-described non-lead flat package type semiconductor device is mounted on a mounting board, a short circuit phenomenon occurs between terminals of the semiconductor device or between wiring patterns of the mounting board. There was a problem of doing.

【0007】そこで、本発明の目的は、実装基板に実装
した際に、突出端子間で、又は実装基板の配線パターン
間で短絡現象を生じないようなノンリード・フラットパ
ッケージ型半導体装置を提供することである。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-lead flat package type semiconductor device which does not cause a short circuit phenomenon between protruding terminals or between wiring patterns of a mounting substrate when mounted on a mounting substrate. It is.

【0008】[0008]

【課題を解決するための手段】本発明者は、半導体装置
の端子間で、又は実装基板の配線パターン間で短絡現象
が発生するという問題を子細に検討したところ、図9に
示すように、クリームはんだ19aが、半導体装置10
と実装基板19間で押し潰され、クリームはんだ19a
同士が接触して、はんだブリッジ19bが生じ、その結
果、半導体装置の突出端子14間、又は実装基板19の
配線パターン間で短絡が発生したりしていることを突き
止めた。尚、図9は、図8の“A“の拡大図である。そ
して、はんだブリッジ19bが発生する原因は、金型を
使って半導体素子を樹脂封止した際に、金型間に突出端
子を挟んだような状態で金型内に樹脂を注入し、硬化さ
せているので、図10に示すように、樹脂15が突出端
子14間に充満している。そのために、過剰なクリーム
はんだが逃げる余地がなく、そのために横に拡がって、
はんだブリッジが生じることが判った。尚、図10は、
図5の“A“の拡大図である。そこで、本発明者は、突
出端子14間の樹脂15を除去して、過剰なクリームは
んだが逃げる余地を突出端子14間に設けることによ
り、はんだブリッジの発生を防止し、はんだブリッジに
起因する短絡現象を発生させないようにすることを着想
し、実験を重ねて本発明を完成するに到った。
The inventor of the present invention has studied in detail the problem that a short circuit phenomenon occurs between terminals of a semiconductor device or between wiring patterns of a mounting board. As shown in FIG. The cream solder 19a is
And the mounting board 19 are crushed and the cream solder 19a
The solder bridges 19b were generated due to the mutual contact, and as a result, it was determined that a short circuit occurred between the protruding terminals 14 of the semiconductor device or between the wiring patterns of the mounting board 19. FIG. 9 is an enlarged view of “A” in FIG. The cause of the occurrence of the solder bridge 19b is that when the semiconductor element is sealed with a resin using a mold, the resin is injected into the mold in a state where the protruding terminals are sandwiched between the molds, and the resin is cured. Therefore, as shown in FIG. 10, the resin 15 is filled between the protruding terminals 14. Therefore, there is no room for excess cream solder to escape, so it spreads sideways,
It was found that solder bridges occurred. In addition, FIG.
FIG. 6 is an enlarged view of “A” in FIG. 5. Therefore, the present inventor has removed the resin 15 between the protruding terminals 14 and provided a space between the protruding terminals 14 to allow excess cream solder to escape, thereby preventing the occurrence of solder bridges and short-circuiting caused by the solder bridges. With the idea of preventing the phenomenon from occurring, the present inventors have completed the present invention through repeated experiments.

【0009】上記目的を達成するために、本発明に係る
ノンリード・フラットパッケージ型半導体装置は、樹脂
又はセラミック等の封止材により半導体素子を内部に封
止してなる封止体の周縁から、実装基板との接続用端子
として多数の短い突出端子を封止体の下面と同じ面上で
外方に向けて突出させた、ノンリード・フラットパッケ
ージ型半導体装置において、短い突出端子は、突出端子
間に樹脂、又はセラミック等の封止材を保持することな
く、突出端子外周面を封止体から露出させ、かつ、突出
端子外周面上に金属皮膜を備えていることを特徴として
いる。
In order to achieve the above object, a non-leaded flat package type semiconductor device according to the present invention is characterized in that a semiconductor element is sealed inside with a sealing material such as resin or ceramic. In a non-lead flat package type semiconductor device in which a number of short protruding terminals are protruded outward on the same surface as the lower surface of a sealing body as terminals for connection with a mounting board, the short protruding terminals are connected between the protruding terminals. In addition, the outer peripheral surface of the protruding terminal is exposed from the sealing body without holding a sealing material such as resin or ceramic, and a metal film is provided on the outer peripheral surface of the protruding terminal.

【0010】本発明に係るノンリード・フラットパッケ
ージ型半導体装置の突出端子は、その大きさが、実装基
板に実装する際、実装基板の配線パターンとの接続用端
子として機能する必要最小限の大きさである。突出端子
に設けた金属皮膜は、封止材により半導体素子を内部に
封止した後に、突出端子間から封止材を除去して突出端
子外周面を露出させ、次いで突出端子にメッキ処理を施
して成膜した金属皮膜であって、例えばはんだ接合の際
のはんだ被着性を高める皮膜、耐腐食性金属皮膜等を言
う。
The size of the protruding terminal of the non-lead flat package type semiconductor device according to the present invention is the minimum necessary size that functions as a terminal for connection with the wiring pattern of the mounting board when mounted on the mounting board. It is. The metal film provided on the protruding terminals is formed by sealing the semiconductor element inside with a sealing material, removing the sealing material from between the protruding terminals to expose the outer peripheral surface of the protruding terminals, and then plating the protruding terminals. A metal film formed by deposition, for example, a film that enhances solder adherence at the time of solder joining, a corrosion-resistant metal film, and the like.

【0011】[0011]

【発明の実施の形態】以下に、実施形態例を挙げ、添付
図面を参照して、本発明の実施の形態を具体的かつ詳細
に説明する。実施形態例 本実施形態例は、本発明に係るノンリード・フラットパ
ッケージ型半導体装置(以下、簡単に半導体装置と言
う)の実施形態の一例であって、図1は本実施形態例の
半導体装置の平面図、図2は本実施形態例の半導体装置
の斜視図、図3(a)は突出端子の縦断面図、及び図3
(b)は突出端子の横断面図である。尚、図1から図3
に示した部位のうち図5から図7に示すものと同じもの
には同じ符号を付して、その説明を省略する。本実施形
態例のノンリード・フラットパッケージ型半導体装置2
0(以下、簡単に半導体装置20と言う)は、図1に示
すように、突出端子22の構成を除いて、前述の従来の
ノンリード・フラットパッケージ型半導体装置10の構
成と同じ構成を備えている。
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment Example This embodiment is an example of an embodiment of a non-leaded flat package type semiconductor device (hereinafter simply referred to as a semiconductor device) according to the present invention, and FIG. FIG. 2 is a plan view, FIG. 2 is a perspective view of the semiconductor device of this embodiment, FIG.
(B) is a cross-sectional view of the protruding terminal. 1 to 3
The same parts as those shown in FIGS. 5 to 7 are denoted by the same reference numerals, and the description thereof will be omitted. Non-lead flat package type semiconductor device 2 of this embodiment
0 (hereinafter simply referred to as a semiconductor device 20) has the same configuration as that of the above-described conventional non-lead flat package type semiconductor device 10 except for the configuration of the protruding terminal 22, as shown in FIG. I have.

【0012】半導体装置20は、図1及び図2に示すよ
うに、実装基板との接続用端子として、樹脂又はセラミ
ック等の封止材で内部の半導体素子を封止したほぼ正四
角柱状の封止体12の4辺から外方に向けて極く短く突
出した多数の突出端子22を備えている。突出端子22
は、それぞれ、封止体14の下面と同じ面上で封止体1
4の四辺の各辺に直交して突出している。本実施形態例
の半導体装置20では、突出端子22は、図1及び図2
に示すように、突出端子22間に樹脂等の封止材を保持
することなく、突出端子22の外周面が封止体12から
露出している。また、図3(a)及び(b)に示すよう
に、突出端子22の端子基体22a上に、はんだ被着性
を高め、かつ耐腐食性に優れた金属皮膜22bがメッキ
されている。
As shown in FIG. 1 and FIG. 2, the semiconductor device 20 has a substantially square prism-like sealing shape in which the internal semiconductor element is sealed with a sealing material such as resin or ceramic as a terminal for connection with a mounting substrate. A plurality of protruding terminals 22 that protrude outward from four sides of the stop body 12 extremely short are provided. Projecting terminal 22
Respectively, on the same surface as the lower surface of the sealing body 14,
4 project perpendicularly to each of the four sides. In the semiconductor device 20 of the present embodiment, the protruding terminals 22 correspond to those shown in FIGS.
As shown in FIG. 5, the outer peripheral surface of the protruding terminal 22 is exposed from the sealing body 12 without holding a sealing material such as a resin between the protruding terminals 22. Further, as shown in FIGS. 3A and 3B, a metal film 22b that enhances solder adherence and has excellent corrosion resistance is plated on the terminal base 22a of the protruding terminal 22.

【0013】本実施形態例の半導体装置20は、金型を
使って樹脂等の封止材で半導体素子を封止した後、突出
端子22の間に充満する樹脂等の封止材をパンチング金
型等を使って除去し、突出端子22を封止体12から露
出させる。次いで、露出した突出端子22の端子基材2
2a上にメッキ法等により金属皮膜22bを被着させ
て、半導体装置20を完成する。
In the semiconductor device 20 of this embodiment, after sealing the semiconductor element with a sealing material such as a resin using a mold, a sealing material such as a resin filled between the protruding terminals 22 is punched. The protrusion terminal 22 is removed from the sealing body 12 by using a mold or the like. Next, the terminal substrate 2 of the exposed protruding terminal 22
A metal film 22b is deposited on 2a by a plating method or the like to complete the semiconductor device 20.

【0014】本実施形態例の半導体装置20を実装基板
19に実装する際には、半導体装置10は、実装基板1
9の配線パターン(図示せず)上のクリームはんだ19
aを被着させたはんだランド上に突出端子22を位置合
わせし、リフロー法等により突出端子22を配線パター
ンにはんだ接合させる。
When the semiconductor device 20 of this embodiment is mounted on the mounting board 19, the semiconductor device 10
Cream solder 19 on the wiring pattern 9 (not shown)
The protruding terminal 22 is positioned on the solder land on which a is attached, and the protruding terminal 22 is soldered to the wiring pattern by a reflow method or the like.

【0015】はんだ接合の際、本実施形態例では、突出
端子22の間に樹脂が存在しないので、クリームはんだ
19aが、図4に示すように、突出端子22の側面に回
り込む。よって、従来のように、クリームはんだ19a
同士がはんだブリッジを形成して、短絡現象を発生させ
ることなく、しかも、実装基板19の配線パターンとの
電気的及び機械的接続の強度を高めることができる。な
お、図4は、半導体装置を実装基板上に実装する際のは
んだ接合時の図1の線I−Iでの突出端子とはんだとの
関係を示す説明図である。また、本実施形態例の半導体
装置20の突出端子22は、はんだ被着性を高め、かつ
耐腐食性に優れた金属皮膜22bがメッキされているの
で、はんだとの馴染みが良く、また、耐腐食性に優れ、
長期間使用の信頼性が高い。
At the time of solder joining, in the present embodiment, since no resin exists between the protruding terminals 22, the cream solder 19a wraps around the side surface of the protruding terminal 22, as shown in FIG. Therefore, as in the conventional case, the cream solder 19a
A solder bridge is formed between them, and a short circuit phenomenon does not occur, and the strength of electrical and mechanical connection with the wiring pattern of the mounting board 19 can be increased. FIG. 4 is an explanatory diagram showing the relationship between the protruding terminals along line II of FIG. 1 and the solder at the time of soldering when the semiconductor device is mounted on the mounting board. Further, the protruding terminals 22 of the semiconductor device 20 of the present embodiment are plated with a metal film 22b which enhances solder adherence and is excellent in corrosion resistance, so that the protrusions 22 are well adapted to solder and have good resistance to solder. Excellent corrosiveness,
High reliability for long-term use.

【0016】[0016]

【発明の効果】本発明によれば、ノンリード・フラット
パッケージ型半導体装置の実装基板との接続用端子とし
て、突出端子間に樹脂、又はセラミック等の封止材を保
持することなく、突出端子外周面を封止体から露出さ
せ、かつ、金属皮膜を有する突出端子を設けているの
で、はんだ接合の際、はんだが、突出端子の側面に回り
込む。よって、従来のように、はんだ同士がはんだブリ
ッジを形成して、短絡現象を発生させることなく、しか
も、実装基板の配線パターンとの電気的及び機械的接続
の強度を高めることができる。また、はんだ被着性を高
め、かつ耐腐食性に優れた金属皮膜を突出端子に設ける
ことにより、はんだとの馴染みが良く、はんだ接合性及
び耐腐食性に優れ、長期間使用の信頼性が高いノンリー
ド・フラットパッケージ型半導体装置を実現することが
できる。
According to the present invention, as a terminal for connection with a mounting substrate of a non-lead flat package type semiconductor device, a resin or a sealing material such as ceramic is not held between the protruding terminals and the outer periphery of the protruding terminal is maintained. Since the surface is exposed from the sealing body and the protruding terminal having the metal film is provided, the solder goes around the side surface of the protruding terminal at the time of soldering. Therefore, unlike the related art, it is possible to increase the strength of the electrical and mechanical connection between the solder and the wiring pattern of the mounting board without causing a solder bridge to form a short circuit phenomenon. In addition, by providing a metal film with high corrosion resistance and excellent corrosion resistance on the protruding terminals, it has good compatibility with solder, excellent solder jointability and corrosion resistance, and long-term reliability. A high non-lead flat package type semiconductor device can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係るノンリード・フラットパッケージ
型半導体装置の実施形態例の平面図である。
FIG. 1 is a plan view of an embodiment of a non-leaded flat package type semiconductor device according to the present invention.

【図2】本発明に係るノンリード・フラットパッケージ
型半導体装置の実施形態例の斜視図である。
FIG. 2 is a perspective view of an embodiment of a non-lead flat package type semiconductor device according to the present invention.

【図3】図3(a)は突出端子の縦断面図、及び図3
(b)は突出端子の横断面図である。
FIG. 3A is a longitudinal sectional view of a protruding terminal, and FIG.
(B) is a cross-sectional view of the protruding terminal.

【図4】実施形態例の半導体装置を実装基板上に実装す
る際のはんだ接合時の図1の線I−Iでの突出端子とは
んだとの関係を示す説明図である。
4 is an explanatory diagram showing a relationship between a protruding terminal and a solder at line II in FIG. 1 at the time of soldering when the semiconductor device of the embodiment is mounted on a mounting board.

【図5】図5(a)及び図5(b)は、それぞれ、従来
のノンリード・フラットパッケージ型半導体装置の平面
図、及び側面図である。
FIGS. 5A and 5B are a plan view and a side view, respectively, of a conventional non-lead flat package type semiconductor device.

【図6】従来のノンリード・フラットパッケージ型半導
体装置の斜視図である。
FIG. 6 is a perspective view of a conventional non-lead flat package type semiconductor device.

【図7】図7は図5(a)の線II−IIでの断面図であ
る。
FIG. 7 is a cross-sectional view taken along line II-II in FIG.

【図8】従来の半導体装置を実装基板上に実装する際の
はんだ接合時の突出端子とはんだとの関係を示す説明図
である。
FIG. 8 is an explanatory diagram showing a relationship between a protruding terminal and solder at the time of soldering when a conventional semiconductor device is mounted on a mounting board.

【図9】図8の“A“の拡大図である。FIG. 9 is an enlarged view of “A” in FIG. 8;

【図10】図5の“B“の拡大図である。FIG. 10 is an enlarged view of “B” in FIG. 5;

【符号の説明】[Explanation of symbols]

10……従来のノンリード・フラットパッケージ型半導
体装置、12……封止体、14……突出端子、15……
端子間樹脂、16……ダイパッド、17……半導体チッ
プ、18……ボンディングワイヤ、19……実装基板、
19a……はんだ、20……実施形態例のノンリード・
フラットパッケージ型半導体装置、22……突出端子、
22a……端子基体、22b……金属皮膜。
10 ... conventional non-lead flat package type semiconductor device, 12 ... sealing body, 14 ... protruding terminal, 15 ...
Resin between terminals, 16 die pad, 17 semiconductor chip, 18 bonding wire, 19 mounting board,
19a: solder, 20: non-lead of the embodiment example
Flat package type semiconductor device, 22 projecting terminal,
22a ... terminal base, 22b ... metal film.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 樹脂又はセラミック等の封止材により半
導体素子を内部に封止してなる封止体の周縁から、実装
基板との接続用端子として多数の短い突出端子を封止体
の下面と同じ面上で外方に向けて突出させた、ノンリー
ド・フラットパッケージ型半導体装置において、 短い突出端子は、突出端子間に樹脂、又はセラミック等
の封止材を保持することなく、突出端子外周面を封止体
から露出させ、かつ、突出端子外周面上に金属皮膜を備
えていることを特徴とするノンリード・フラットパッケ
ージ型半導体装置。
1. A large number of short protruding terminals serving as terminals for connection with a mounting substrate are formed on the lower surface of a sealing body from the periphery of the sealing body in which a semiconductor element is sealed with a sealing material such as resin or ceramic. In a non-leaded flat package type semiconductor device, which protrudes outward on the same surface as the above, the short protruding terminal is formed without holding a sealing material such as resin or ceramic between the protruding terminals, and A non-lead flat package type semiconductor device characterized in that a surface is exposed from a sealing body and a metal film is provided on an outer peripheral surface of a protruding terminal.
【請求項2】 金属皮膜が、封止材により半導体素子を
内部に封止した後に、突出端子間から封止材を除去して
突出端子外周面を露出させ、次いで突出端子にメッキ処
理を施して成膜した金属皮膜であることを特徴とする請
求項1に記載のノンリード・フラットパッケージ型半導
体装置。
2. After the metal film seals the semiconductor element inside with the sealing material, the sealing material is removed from between the protruding terminals to expose the outer peripheral surface of the protruding terminal, and then the protruding terminal is plated. 2. The non-lead flat package type semiconductor device according to claim 1, wherein the semiconductor device is a metal film formed by deposition.
JP10668699A 1999-04-14 1999-04-14 Non-lead flat-package type semiconductor device Pending JP2000299400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10668699A JP2000299400A (en) 1999-04-14 1999-04-14 Non-lead flat-package type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10668699A JP2000299400A (en) 1999-04-14 1999-04-14 Non-lead flat-package type semiconductor device

Publications (1)

Publication Number Publication Date
JP2000299400A true JP2000299400A (en) 2000-10-24

Family

ID=14439948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10668699A Pending JP2000299400A (en) 1999-04-14 1999-04-14 Non-lead flat-package type semiconductor device

Country Status (1)

Country Link
JP (1) JP2000299400A (en)

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Publication number Priority date Publication date Assignee Title
US7410834B2 (en) 2003-12-25 2008-08-12 Renesas Technology Corp. Method of manufacturing a semiconductor device
JP2010010187A (en) * 2008-06-24 2010-01-14 Renesas Technology Corp Method of manufacturing semiconductor integrated circuit device
KR101408879B1 (en) 2008-06-13 2014-06-17 삼성전자주식회사 Chip having side protrusion terminal and package using the chip
JP2014143437A (en) * 2014-04-03 2014-08-07 Renesas Electronics Corp Semiconductor device
KR20140100904A (en) 2013-02-07 2014-08-18 세이코 인스트루 가부시키가이샤 Semiconductor device
US9087850B2 (en) 2009-07-06 2015-07-21 Renesas Electronics Corporation Method for manufacturing semiconductor device
JP2020025049A (en) * 2018-08-08 2020-02-13 新日本無線株式会社 Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7410834B2 (en) 2003-12-25 2008-08-12 Renesas Technology Corp. Method of manufacturing a semiconductor device
KR101408879B1 (en) 2008-06-13 2014-06-17 삼성전자주식회사 Chip having side protrusion terminal and package using the chip
JP2010010187A (en) * 2008-06-24 2010-01-14 Renesas Technology Corp Method of manufacturing semiconductor integrated circuit device
US8026130B2 (en) 2008-06-24 2011-09-27 Renesas Electronics Corporation Method for manufacturing a semiconductor integrated circuit device
US8338927B2 (en) 2008-06-24 2012-12-25 Renesas Electronics Corporation Semiconductor device with the leads projected from sealing body
US9087850B2 (en) 2009-07-06 2015-07-21 Renesas Electronics Corporation Method for manufacturing semiconductor device
US9263274B2 (en) 2009-07-06 2016-02-16 Renesas Electronics Corporation Method for manufacturing semiconductor device
KR20140100904A (en) 2013-02-07 2014-08-18 세이코 인스트루 가부시키가이샤 Semiconductor device
JP2014143437A (en) * 2014-04-03 2014-08-07 Renesas Electronics Corp Semiconductor device
JP2020025049A (en) * 2018-08-08 2020-02-13 新日本無線株式会社 Semiconductor device
JP7156673B2 (en) 2018-08-08 2022-10-19 日清紡マイクロデバイス株式会社 semiconductor equipment

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