JPS6169848U - - Google Patents

Info

Publication number
JPS6169848U
JPS6169848U JP1984154198U JP15419884U JPS6169848U JP S6169848 U JPS6169848 U JP S6169848U JP 1984154198 U JP1984154198 U JP 1984154198U JP 15419884 U JP15419884 U JP 15419884U JP S6169848 U JPS6169848 U JP S6169848U
Authority
JP
Japan
Prior art keywords
pellet
loss
temperature
pellets
high voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984154198U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984154198U priority Critical patent/JPS6169848U/ja
Publication of JPS6169848U publication Critical patent/JPS6169848U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
JP1984154198U 1984-10-15 1984-10-15 Pending JPS6169848U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984154198U JPS6169848U (enrdf_load_stackoverflow) 1984-10-15 1984-10-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984154198U JPS6169848U (enrdf_load_stackoverflow) 1984-10-15 1984-10-15

Publications (1)

Publication Number Publication Date
JPS6169848U true JPS6169848U (enrdf_load_stackoverflow) 1986-05-13

Family

ID=30712192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984154198U Pending JPS6169848U (enrdf_load_stackoverflow) 1984-10-15 1984-10-15

Country Status (1)

Country Link
JP (1) JPS6169848U (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220053488A (ko) 2020-10-22 2022-04-29 신에쓰 가가꾸 고교 가부시끼가이샤 오늄염, 화학 증폭 레지스트 조성물 및 패턴 형성 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220053488A (ko) 2020-10-22 2022-04-29 신에쓰 가가꾸 고교 가부시끼가이샤 오늄염, 화학 증폭 레지스트 조성물 및 패턴 형성 방법

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