JPS6168528U

JPS6168528U -

Info

Publication number: JPS6168528U
Application number: JP15282584U
Authority: JP
Priority date: 1984-10-09
Filing date: 1984-10-09
Publication date: 1986-05-10

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例の接続図、第２図
及び第３図はこの考案の一実施例の説明に用いる
波形図である。３：入力端子、４：電源端子、９：シユミツト
回路、１０：出力端子。 FIG. 1 is a connection diagram of an embodiment of this invention, and FIGS. 2 and 3 are waveform diagrams used to explain an embodiment of this invention. 3: Input terminal, 4: Power supply terminal, 9: Schmitt circuit, 10: Output terminal.

Claims

[Scope of utility model registration request]

A first MOS transistor and a second MOS transistor are connected in series between a first reference potential point and a second reference potential point, and a third MOS transistor is connected between the first and second reference potential points. A transistor, a fourth MOS transistor, and a fifth MOS transistor are connected in series, and the gate of the first MOS transistor and the gate of the third MOS transistor having a conductance smaller than the conductance of the first MOS transistor are connected in series. The connection point between the first and second MOS transistors and the second MOS transistor are connected to an input terminal to which a DC voltage is supplied.
The gate of the transistor and the gate of the fifth MOS transistor are connected, a capacitor is connected between the connection point of the third MOS transistor and the fourth MOS transistor and the first or second reference potential point, and the A circuit for inverting the output at first and second threshold levels is inserted between the connection point of the third and fourth MOS transistors and the gate of the fourth MOS transistor; A voltage-controlled oscillator whose output is taken from a circuit that inverts the output at a threshold level.