JPS6163061A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6163061A JPS6163061A JP12934685A JP12934685A JPS6163061A JP S6163061 A JPS6163061 A JP S6163061A JP 12934685 A JP12934685 A JP 12934685A JP 12934685 A JP12934685 A JP 12934685A JP S6163061 A JPS6163061 A JP S6163061A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- type
- semiconductor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 238000000034 method Methods 0.000 abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000005669 field effect Effects 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000001947 vapour-phase growth Methods 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置、特に半導体集積回路装置におけ
る半導体基板上の多層配線に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multilayer wiring on a semiconductor substrate in a semiconductor device, particularly a semiconductor integrated circuit device.
従来の半導体集積回路装置における配線は所定の回路素
子が半導体基板の一生平面上に形成され、この主平面上
に覆われた絶縁層上にアルミニウム等“の金属層や、シ
リコン等の半導体層を蒸着法、スパッタリング法、ある
いは気相成長法等によって形成し、しかる後写真蝕刻法
等で配線路となるべき部分の金属層あるいは半導体層の
みを残し他の部分の金ｉＷＪあるいは半導体層を除去す
ることにより配線を形成していた。必要に応じて上記半
゛導体装置の表面が直接外気に触れるのを避け
る為、外部電極の取り出し部分を除いて全面に絶縁物層
を更に被覆していた。この従来の半導体装置の配線では
、少くとも配線路を形成してから絶縁物層を被覆するま
での製造工程に於いて配線路の側面が露出しており１．
さらに装置完成後も配線路上を被覆する絶縁物層を有し
ないものは勿論のこと、配線路上に絶縁物層を有するも
のでも完全に強固で緻密な絶縁物層が得難い為、この配
線路の側面から汚れが侵入し、半導体基板内の素子の安
定性を損ね半導体集積回路装置の信頼性を低下させてい
た。また所定の回路素子が形成された半導体基板の一主
面上に絶縁層を介して第一の金属層や半導体層を形成し
、写真蝕刻法によって第一の配線路を形成し、さらにそ
の上を絶縁物層で被覆してから第二の金属層や半導体層
を形成し、再び写真蝕刻法等によって第二の配線路を形
成する従来の多層配線構造としたものがある。この場合
は第一の配線路自体のＨさによる段が存在し、この上に
絶縁物ｎを被覆する際に絶縁物層がこの段の所で薄くな
ったり切れたりして、第一の配線路と第二の配線路とが
短絡するおそれがあった。さらに第二の金属層や半導体
層を形成する際に第一の配線路自体の段の所で薄くなっ
たり切れたりして、あるいは写真蝕刻法等で第二の配線
路を形成する際に第一の配線路の段の所でエツチングが
早く進み第二の配線路が断紗したりするという不都合も
存在していた。これ等種々の理由から、従来の半導体装
置においては信頼性の高い多層配Ｉｎ構造のものを歩留
りよく作製することはほとんど不可能でありた。In wiring in conventional semiconductor integrated circuit devices, predetermined circuit elements are formed on a flat surface of a semiconductor substrate, and a metal layer such as aluminum or a semiconductor layer such as silicon is formed on an insulating layer covering this main surface. It is formed by a vapor deposition method, a sputtering method, a vapor phase growth method, etc., and then a photolithography method is used to remove the gold iWJ or semiconductor layer in other parts, leaving only the metal layer or semiconductor layer in the portion that will become the wiring path. In order to prevent the surface of the semiconductor device from coming into direct contact with the outside air, if necessary, the entire surface of the semiconductor device was further coated with an insulating layer except for the areas where the external electrodes were taken out. In the wiring of this conventional semiconductor device, the side surfaces of the wiring path are exposed at least during the manufacturing process from forming the wiring path to coating the insulating layer.1.
Furthermore, even after the device is completed, it is difficult to obtain a completely strong and dense insulating layer, not only in devices that do not have an insulating layer covering the wiring path, but also in devices that have an insulating layer on the wiring path. Dirt enters the semiconductor substrate, impairing the stability of the elements within the semiconductor substrate, and reducing the reliability of the semiconductor integrated circuit device. Further, a first metal layer or a semiconductor layer is formed on one main surface of the semiconductor substrate on which a predetermined circuit element is formed, via an insulating layer, a first wiring path is formed by photolithography, and then There is a conventional multilayer wiring structure in which a second metal layer or a semiconductor layer is formed after covering the wiring with an insulating layer, and then a second wiring path is formed again by photolithography or the like. In this case, there is a step due to the H height of the first wiring path itself, and when covering this with the insulator n, the insulating layer becomes thinner or breaks at this step, and the first wiring path There was a risk that the path and the second wiring path would be short-circuited. Furthermore, when forming the second metal layer or semiconductor layer, the first wiring path itself may become thin or cut at a step, or when forming the second wiring path by photolithography or the like. There was also the problem that etching progressed quickly at the step of the first wiring path, causing the second wiring path to become gauzy. For these various reasons, it has been almost impossible to manufacture a highly reliable multilayer In structure with a high yield in conventional semiconductor devices.
この発明の目的は半導体装置の製造工程に於いて、ある
いは装置完成後の外部からの汚れが侵入し難く、安定か
つ信頼性が高く、かつ配線自体の厚さの段による凹凸が
無く、はぼ平坦な表面を持ち、多層配線構造としても安
定で信頼性が高く、製造歩留りのよい半導体装置となし
得る半導体装置の配線を提供するにある。The purpose of this invention is to provide a semiconductor device that is difficult to infiltrate with dirt from the outside during the manufacturing process of the semiconductor device or after the device is completed, is stable and reliable, and is free from unevenness caused by steps in the thickness of the wiring itself. It is an object of the present invention to provide wiring for a semiconductor device that has a flat surface, is stable and highly reliable even as a multilayer wiring structure, and can be made into a semiconductor device with a high manufacturing yield.
この発明の特徴は、半導体基板に設けられた不純物領域
に接続せる半導体層がこの半導体基板上に設けられた絶
縁層上を延在し、その半導体層は絶縁層上でＰＮ接合に
よって分離された下層配線路とした多層の配線路を有す
る半導体装置にある。The feature of this invention is that a semiconductor layer connected to an impurity region provided on a semiconductor substrate extends over an insulating layer provided on this semiconductor substrate, and the semiconductor layer is separated by a PN junction on the insulating layer. A semiconductor device has a multilayer wiring path as a lower layer wiring path.
この発明は半導体基板上に絶縁膜を介して設けられたシ
リコンゲート電極に接続せる半導体層がＰＮ接合によっ
て分離されて配線路を形成してこの配線路上に絶縁膜を
被着し多層の配線路を形成することもできる。In this invention, a semiconductor layer connected to a silicon gate electrode provided on a semiconductor substrate through an insulating film is separated by a PN junction to form a wiring path, and an insulating film is coated on the wiring path to form a multilayer wiring path. can also be formed.
すなわち、この発明の半導体装置の配線は、所定の回路
素子が形成された半導体基板の一主面上に絶縁層を介し
て、適当な比抵抗及び適当な導電量の半導体層が形成さ
れる。この半導体層にはこれと逆導電型の部分の配線路
が設ゆられる。この配線路間はＰ−Ｎ接合により電気的
に分離される。That is, in the wiring of the semiconductor device of the present invention, a semiconductor layer having an appropriate specific resistance and an appropriate amount of conductivity is formed on one main surface of a semiconductor substrate on which predetermined circuit elements are formed, with an insulating layer interposed therebetween. A wiring path of a conductivity type opposite to this semiconductor layer is provided. These wiring paths are electrically separated by a PN junction.
この半導体装置の配線は半導体層自体ＫＰＮ接合にて分
離された配線路が形成されるために配線路の側面は露出
せず、しかもその配線が形成された半導体層を熱酸化す
れば配線路上を強固で緻密な熱酸化物層で被覆出来る。In the wiring of this semiconductor device, wiring paths separated by the semiconductor layer itself are formed by KPN junctions, so the side surfaces of the wiring paths are not exposed.Moreover, if the semiconductor layer in which the wiring is formed is thermally oxidized, the wiring paths can be removed. Can be coated with a strong and dense thermal oxide layer.
このようにすれば外部より汚れが侵入し難い安定性と高
い信頼性が保障された半導体装置となる。さらに上記よ
り明らかな如く配線路自体の厚さによる凹凸は全く無（
、半導体装置表面に存在する凹凸は半導体基板自体の凹
凸のみでありて、はぼ平坦なものとなる。従ってこの半
導体層の配線路を第一の配線路とし、この上に絶縁物層
を被覆してその上にさらに第二の配線路を形成する多層
配線構造とする時は、第１の配線路上の絶縁物層は一様
かつ均一に形成出来るので、第一の配線路と第二の配線
路との短絡は起らず、また第二の配線路を形成する為の
写真蝕刻法等が容易に正確に出来るので第二の配線路の
厚さも一様かつ均一と・なり、不都合なエツチング等に
よる断線も生じない。この第二の配線路は従来の金属層
や半導体層を写真蝕刻法等により形成することも出来る
し、あるいは本発明の第一の配線路と同様の構造によっ
て形成することも可能である。後者の構造とするならば
、半導体装置表面の凹凸を何ら増すことなく配線路を何
層にも重ねることも可能である。即ち本発明半導体装置
の配線によれば３層以上の多層配線構造としても信頼性
の高い半導体装置が容易にかつ歩留りよく実現できる。In this way, the semiconductor device is guaranteed to be stable and highly reliable, making it difficult for dirt to enter from the outside. Furthermore, as is clear from the above, there is no unevenness due to the thickness of the wiring path itself (
The unevenness existing on the surface of the semiconductor device is only the unevenness of the semiconductor substrate itself, and is almost flat. Therefore, when forming a multilayer wiring structure in which the wiring path in the semiconductor layer is used as the first wiring path, and a second wiring path is further formed on top of this by covering the insulating layer, it is necessary to Since the insulating layer can be formed evenly and uniformly, short circuits between the first wiring path and the second wiring path do not occur, and photolithography, etc., for forming the second wiring path is easy. Since the second wiring path can be formed accurately, the thickness of the second wiring path is also uniform and uniform, and there is no possibility of disconnection due to inconvenient etching or the like. The second wiring path can be formed by conventional photolithography using a metal layer or semiconductor layer, or can be formed by a structure similar to that of the first wiring path of the present invention. If the latter structure is adopted, it is possible to stack wiring paths in many layers without increasing the unevenness of the surface of the semiconductor device. That is, according to the wiring of the semiconductor device of the present invention, a highly reliable semiconductor device can be easily realized with a high yield even if it has a multilayer wiring structure of three or more layers.
この発明の半導体装置の配線は絶縁膜を介して設けられ
たシリコンゲート電極に接続することもできる。The wiring of the semiconductor device of the present invention can also be connected to a silicon gate electrode provided through an insulating film.
上述の説明より解る様に、この発明は特に絶縁ゲート型
電解効果半導体装置に適用した場合に極めて大きな効果
をあげることができる。以下にいくつかの実施例を挙げ
て図面を参照しながら詳しく説明しよう。As can be seen from the above description, the present invention can produce extremely great effects especially when applied to an insulated gate field effect semiconductor device. Hereinafter, several embodiments will be described in detail with reference to the drawings.
実施例１：
第１図はＰチャンネル絶縁ゲート型電界効果トランジス
クの製造工程を示す断面図で同一符号は同一のものを表
わしている。第１図ΔでＮ型単結晶シリコン基板１中１
ｃ Ｐ ｍの拡散領域であるソース領域２とドレイン領
域３とカ；形成され、半導体基板１の上記領域２．３が
形成された主平面上に熱酸化によって二酸化シリコン膜
４が形成される。Embodiment 1: FIG. 1 is a sectional view showing the manufacturing process of a P-channel insulated gate field effect transistor, and the same reference numerals represent the same parts. Figure 1: N-type single crystal silicon substrate 1 in 1 at Δ
A source region 2 and a drain region 3, which are diffusion regions of cPm, are formed, and a silicon dioxide film 4 is formed by thermal oxidation on the main plane of the semiconductor substrate 1 where the regions 2.3 are formed.
ソース領域２とドレイン領域３とにオーミックな接触を
取るために、標準の写真蝕刻法によるマスク及びエツチ
ング技術を用いて二酸化シリコン膜４中に開孔を穿った
後、この上に約１ミクロンのＮｆｆ１シリコン居５を蒸
着、スパッタリング、気相成長等の方法により形成した
。シリコン層５をＮ捜とするにはこの層５の形成段階で
燐等のＮ型不純物を添加するか、あるいは層５を形成し
た後にＮ型不純物を拡散してもよい。To make ohmic contact between the source region 2 and the drain region 3, an aperture of about 1 micron is then etched into the silicon dioxide film 4 using standard photolithographic masking and etching techniques. Nff1 silicon layer 5 was formed by methods such as vapor deposition, sputtering, and vapor phase growth. To make the silicon layer 5 N-containing, an N-type impurity such as phosphorus may be added during the formation of the layer 5, or the N-type impurity may be diffused after the layer 5 is formed.
次にシリコン層５０表面を熱酸化して二酸化シリコン居
６を形成し、標準の写真蝕刻法によるマスクとエツチン
グ技術を用いて配線路（ソース電極、ゲート電極、ドレ
イン電極等）となるべき部分上の熱酸化物層６中に７４
％の写真蝕刻法によるマスクと工７チング技術を用いて
開孔を穿つ。Next, the surface of the silicon layer 50 is thermally oxidized to form a silicon dioxide layer 6, and a standard photolithographic mask and etching technique is used to form a silicon dioxide layer 6 on the portions that are to become wiring paths (source electrode, gate electrode, drain electrode, etc.). 74 in the thermal oxide layer 6 of
Apertures are made using a photolithographic mask and etching technique.
この開孔な通じてボロン等のＰ型不純物をシリコン層５
中に拡散して第１図ｊに示すように配線路（ソース電極
７、ゲート電極８、ドレイン電極９等）を形成する。こ
のようにして配線路７．８．９間はＰ−Ｎ接合により互
に分離される。次に第 ２１図ＩＣＫ示すようにシリコ
ン層５０表面を熱酸化により二酸化シリコン１０で被覆
し、その内部に配線路７．８．９が存在するようになさ
れる。Through these open holes, P-type impurities such as boron are introduced into the silicon layer 5.
It is diffused into the inside to form wiring paths (source electrode 7, gate electrode 8, drain electrode 9, etc.) as shown in FIG. 1J. In this way, the wiring paths 7, 8, 9 are separated from each other by the PN junction. Next, as shown in FIG. 21 (ICK), the surface of the silicon layer 50 is coated with silicon dioxide 10 by thermal oxidation so that wiring paths 7, 8, 9 are present inside it.
この様にして作製した絶縁ゲート型電界効果半導体装置
では、配線路７．８．９はシリコン層５の中に埋ってい
て配線路７．８．９の側面が露出していない。更に配線
路７．８．９上は熱酸化による二酸化シリコン１０が被
覆され、この熱酸化二酸化シリコン１０は蒸着、スパッ
タリング、気相成長等の方法により形成した絶縁層に比
べはるかに強固で緻密であることから、この半導体装置
は非常にすぐれた安定性及び高い信頼性を示した。In the insulated gate field effect semiconductor device manufactured in this way, the wiring paths 7.8.9 are buried in the silicon layer 5, and the side surfaces of the wiring paths 7.8.9 are not exposed. Further, the wiring paths 7,8,9 are coated with silicon dioxide 10 formed by thermal oxidation, and this thermally oxidized silicon dioxide 10 is much stronger and denser than an insulating layer formed by methods such as vapor deposition, sputtering, and vapor phase growth. For this reason, this semiconductor device exhibited excellent stability and high reliability.
多層配線構造とするために第１図Ｃの状態で配線路間の
オーミックな接触旬とるために、Ｆｉ！ｉ酸化物層１０
中に標準の写真蝕刻法による開孔を穿った後、全面にア
ルミニウムを蒸着し、標準の写真蝕刻法によって配線路
１１を形成する（第２図Ａ）。Fi! i oxide layer 10
After drilling holes therein by standard photolithography, aluminum is deposited on the entire surface, and wiring paths 11 are formed by standard photolithography (FIG. 2A).
この上を絶縁Ｆｉｊ１２で被覆した。この様な装置では
配線路１１を形成するため忙アルミニウムを全面蒸着す
る際、装置表面に存在する凹凸は配線路７．８．９では
なく、絶縁物層４による凹凸のみで、はぼ平坦な表面を
有するためアルミニウムの厚さはその一様性と埼−性が
全面に渡って保障され、さらに配線路１１を形成するた
めの写真蝕刻法が容易に正しく出来るので、安定で信頼
性の高い多層配ａ Ｍ造が容易に歩留りよく実現出来た
。This was covered with insulating Fij12. In such a device, when aluminum is deposited on the entire surface to form the wiring path 11, the unevenness existing on the surface of the device is not the wiring path 7, 8, 9, but only the unevenness due to the insulating layer 4, and the surface is almost flat. Since the aluminum has a surface, the uniformity and sharpness of the aluminum is ensured over the entire surface, and furthermore, the photolithography method for forming the wiring path 11 can be easily and accurately performed, making it stable and reliable. Multi-layer A M construction was easily realized with good yield.
実施例２：
多層配線の他の例としては′：Ａ艶例１の第１図・Ｃの
状態で配線路間のオーミックな接触を取るために熱酸化
物層１０中に標準の写真蝕刻法による開孔を穿った後、
先にシリコンＷＩ５及び配線路７．８．９を形成する際
に説明したと同様の方法を用いて第２図Ｂに示すように
シリコンＲ１１３及び配線路１４を熱酸化物ＵＩＯ上に
形成し、その上を熱酸化層１２で被覆した。Embodiment 2: Another example of a multi-layer wiring is ': A standard photo-etching process in the thermal oxide layer 10 to make ohmic contact between the traces in the condition shown in Figure 1C of Example 1. After drilling a hole by
Form silicon R 113 and interconnect 14 on the thermal oxide UIO as shown in FIG. 2B using a method similar to that previously described for forming silicon WI 5 and interconnect 7.8.9; A thermal oxidation layer 12 was coated thereon.
この様な多層配線構造では、多層配線された半導体装置
の表面の凹凸は絶縁物層１４によるもの′のみであり、
多層配線によって何ら増さない。従って配線路を何層に
も重ね合わせることが出来た。In such a multilayer wiring structure, the only unevenness on the surface of the multilayered semiconductor device is due to the insulator layer 14.
There is no increase in multilayer wiring. Therefore, it was possible to overlap wiring paths in multiple layers.
この半導体装置は第２図Ａ）で説明した半導体装置より
もさらによい安定性及び高いＭ粗性を示した。This semiconductor device exhibited better stability and higher M roughness than the semiconductor device described in FIG. 2A).
上記実施例では本発明を絶縁ゲート型電界効果トランジ
スタに適用したが一般に電界効果型半導体装置、電界効
果製半導体集積回路装置等のユニポーラ型装置等いわゆ
るプレーナ型装置に対しては何れへも適用可能である。Although the present invention was applied to an insulated gate field effect transistor in the above embodiment, it is generally applicable to any so-called planar type device such as a unipolar type device such as a field effect semiconductor device or a field effect semiconductor integrated circuit device. It is.
又単結晶シリコン基体の代りに、ゲルマニウム、ガリウ
ム砒素等の半導体材料を用いることが出来、絶縁物層４
としては熱酸化による二酸化シリコンの代りに、熱酸化
、蒸着、スパッタリング、気相成長等により形成し？、
： −酸化シリコン、二酸化シリコン、シリコン窒化物
、アルミナ、リンガラス等を用いることも出来る。さら
に配線層として用いるシリコンＭ５の代りに他のゲルマ
ニウム、肩すウム砒素等の半導体層を、蒸着、スパッタ
リング、気相成長等の方法により形成したものを用いる
ことも出来る。本発明の配線構造と従来の配線構造とを
一つの半導体装置内で部分的に組み合わせて用いること
も可能である。Also, instead of the single crystal silicon substrate, semiconductor materials such as germanium, gallium arsenide, etc. can be used, and the insulating layer 4
Instead of silicon dioxide formed by thermal oxidation, is it formed by thermal oxidation, evaporation, sputtering, vapor phase growth, etc.? ,
: - Silicon oxide, silicon dioxide, silicon nitride, alumina, phosphorus glass, etc. can also be used. Further, instead of the silicon M5 used as the wiring layer, it is also possible to use other semiconductor layers such as germanium, arsenic arsenide, etc. formed by methods such as vapor deposition, sputtering, and vapor phase growth. It is also possible to use a partial combination of the wiring structure of the present invention and the conventional wiring structure within one semiconductor device.
第１図および第２図Ａは本発明が適用された多層配線構
造の絶縁ゲート型電界効果トランジスタの一例の製造工
程を示す断面図、第１図および第２図Ｂは本発明が適用
された多層配線構造を有する電界効果型トランジスタの
他の例を示す断面図である。
なお図において、１：半導体基板、２：ソース領域、３
ニドレイン領域、４：絶縁層、５：配線用半導体層、７
．８．９：配線、１０：熱酸化物、である。
第 １８
ｉ’ Ｊ1 and 2A are cross-sectional views showing the manufacturing process of an example of an insulated gate field effect transistor with a multilayer wiring structure to which the present invention is applied, and FIGS. 1 and 2B are sectional views showing the manufacturing process of an example of an insulated gate field effect transistor having a multilayer wiring structure to which the present invention is applied. FIG. 3 is a cross-sectional view showing another example of a field effect transistor having a multilayer wiring structure. In the figure, 1: semiconductor substrate, 2: source region, 3
Nidorain region, 4: Insulating layer, 5: Semiconductor layer for wiring, 7
．． 8.9: Wiring, 10: Thermal oxide. 18th i' J
Claims (2)
して該第１層の配線路上に設けられた第２層の配線路を
有した多層配線の半導体装置において、少なくとも前記
第１層の配線路は前記半導体基板上に設けられた絶縁層
上を延在せる半導体層に設けられたＰＮ接合により分離
されて形成していることを特徴とする半導体装置。(1) In a multilayer wiring semiconductor device having a first layer wiring path and a second layer wiring path provided on the first layer wiring path via an insulating film on a semiconductor substrate, at least the first layer wiring path is provided. 2. A semiconductor device according to claim 1, wherein the wiring paths of the layers are separated by a PN junction provided in a semiconductor layer extending over an insulating layer provided on the semiconductor substrate.
導体層に設けられたＰＮ接合により分離されて形成して
いることを特徴とする特許請求の範囲第（１）項記載の
半導体装置。(2) The wiring path in the second layer is formed separated by a PN junction provided in a semiconductor layer extending over the insulating film. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12934685A JPS6163061A (en) | 1985-06-14 | 1985-06-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12934685A JPS6163061A (en) | 1985-06-14 | 1985-06-14 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP367481A Division JPS56158455A (en) | 1981-01-12 | 1981-01-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6163061A true JPS6163061A (en) | 1986-04-01 |
Family
ID=15007337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12934685A Pending JPS6163061A (en) | 1985-06-14 | 1985-06-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6163061A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1238688A (en) * | 1968-01-29 | 1971-07-07 | ||
| JPS5513137A (en) * | 1978-07-17 | 1980-01-30 | Tokuyama Soda Co Ltd | Method and apparatus for electric dialysis |
-
1985
- 1985-06-14 JP JP12934685A patent/JPS6163061A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1238688A (en) * | 1968-01-29 | 1971-07-07 | ||
| JPS5513137A (en) * | 1978-07-17 | 1980-01-30 | Tokuyama Soda Co Ltd | Method and apparatus for electric dialysis |
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