JPS6162439U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a reset circuit according to an embodiment of the present invention, FIGS. 2 a to f are timing diagrams used to explain the operation of the circuit, and FIG. 3 is a circuit configuration diagram of a conventional reset circuit. FIGS. 4a to 4d are timing diagrams used to explain the operation of the circuit. DESCRIPTION OF SYMBOLS 1...timing output circuit, 2...power supply, 3...logic circuit, 4...clock oscillator, 5...switch, 6...
Clock detection circuit, 61...Band pass filter, 6
2... Rectifier, 63... Level determiner, 7... AND circuit.

Claims (1)

[Claims for Utility Model Registration] (1) In a reset circuit that resets the operating state of a logic circuit that operates in synchronization with a clock signal, the oscillation frequency of the clock signal remains at the normal frequency continuously for a certain period of time or more from the time the power is turned on. A reset circuit, characterized in that it sends out a signal that puts at least the logic circuit in a reset state until the reset state is reached. (2) A timing output circuit that detects the output level of the power supply and generates a signal when the output level of the power supply falls below a predetermined level that is higher than the operable level of the logic circuit, and a timing output circuit that detects the output level of the power supply and generates a signal when the oscillation frequency of the clock signal exceeds a certain period of time. It is characterized by comprising a signal clock detection circuit that generates a signal when the frequency reaches a regular frequency in succession, and an AND circuit that sends out an AND signal of the signals generated by the timing output circuit and the clock detection circuit. A reset circuit according to claim (1) of the utility model registration claim.