JPS621438U - - Google Patents

Info

Publication number
JPS621438U
JPS621438U JP9177385U JP9177385U JPS621438U JP S621438 U JPS621438 U JP S621438U JP 9177385 U JP9177385 U JP 9177385U JP 9177385 U JP9177385 U JP 9177385U JP S621438 U JPS621438 U JP S621438U
Authority
JP
Japan
Prior art keywords
vco
pll circuit
circuit
inactivated
phases
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9177385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9177385U priority Critical patent/JPS621438U/ja
Publication of JPS621438U publication Critical patent/JPS621438U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の一実施例を示す回路図、第
2図はその具体回路例を示す回路図、及び第3図
はPLL回路を説明する為の回路図である。 主な図番の説明、10……ミユーテイング回路
11……VCO、12……周波数制御部、13
……固体共振子、14……発振部、16……検波
回路、17……ミユーテイング解除回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific circuit example thereof, and FIG. 3 is a circuit diagram for explaining a PLL circuit. Explanation of main drawing numbers, 10... Muting circuit, 11 ... VCO, 12... Frequency control section, 13
...Solid resonator, 14...Oscillating section, 16...Detection circuit, 17...Mumuting release circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号とVCOの出力信号との位相が比較さ
れ、位相差に応じた制御信号により前記VCOの
発振周波数が制御されるPLL回路において、前
記VCOの周波数制御部を電源投入から所定時間
不作動にするミユーテイング回路を設けたことを
特徴とするPLL回路。
In a PLL circuit in which the phases of an input signal and an output signal of a VCO are compared and the oscillation frequency of the VCO is controlled by a control signal according to the phase difference, a frequency control section of the VCO is inactivated for a predetermined period of time after power is turned on. A PLL circuit characterized by being provided with a muting circuit.
JP9177385U 1985-06-18 1985-06-18 Pending JPS621438U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9177385U JPS621438U (en) 1985-06-18 1985-06-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9177385U JPS621438U (en) 1985-06-18 1985-06-18

Publications (1)

Publication Number Publication Date
JPS621438U true JPS621438U (en) 1987-01-07

Family

ID=30647957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9177385U Pending JPS621438U (en) 1985-06-18 1985-06-18

Country Status (1)

Country Link
JP (1) JPS621438U (en)

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