JPS6161424A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6161424A JPS6161424A JP18390484A JP18390484A JPS6161424A JP S6161424 A JPS6161424 A JP S6161424A JP 18390484 A JP18390484 A JP 18390484A JP 18390484 A JP18390484 A JP 18390484A JP S6161424 A JPS6161424 A JP S6161424A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- photosensitive resin
- resin film
- polysilicon layer
- plasma treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000011347 resin Substances 0.000 claims abstract description 38
- 229920005989 resin Polymers 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 238000009832 plasma treatment Methods 0.000 claims abstract description 11
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 10
- 239000011737 fluorine Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 50
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 7
- 229910052801 chlorine Inorganic materials 0.000 claims description 7
- 239000000460 chlorine Substances 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical group N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装!製造方法に係り、とくにポリシリ
コン層上に絶縁膜を介して導電層例えば配線用アルミニ
ウム等を形成する工程において、前記ポリシリコン層を
テーパー状に形成することによシ、前記配線用アルミニ
ウム等の段切れを防止する半導体装置製造方法に関する
。[Detailed Description of the Invention] The present invention is a semiconductor device! Regarding the manufacturing method, in particular, in the step of forming a conductive layer such as aluminum for wiring on a polysilicon layer via an insulating film, by forming the polysilicon layer in a tapered shape, the aluminum for wiring, etc. The present invention relates to a semiconductor device manufacturing method that prevents step breakage.
従来、塩素系ガスあるいは弗素系ガスをエツチングガス
として用いた反応性イオンエツチングまたは、塩素系あ
るいは弗素系ガスをエッチングガスとして用い念平行平
板プラズマエツチングによる、ポリシリコン層上の感光
性樹脂膜をマスクとして前記ポリシリコン層をテーパー
エツチングする方法において、−例として8F、を用い
た反応性イオンエツチングによシ前記感光性樹脂膜をマ
スクとして前記ポリシリコン層をアンダーカットさせる
ととKよシ前記ポリシリコン層を第1図(a)の様にテ
ーパー状にエツチングする方法があった。Conventionally, a photosensitive resin film on a polysilicon layer is masked by reactive ion etching using chlorine-based gas or fluorine-based gas as an etching gas, or parallel plate plasma etching using chlorine-based or fluorine-based gas as an etching gas. In the method of taper etching the polysilicon layer, for example, when the polysilicon layer is undercut by reactive ion etching using 8F, and the photosensitive resin film is used as a mask, the polysilicon layer is undercut. There is a method of etching the silicon layer into a tapered shape as shown in FIG. 1(a).
同図で、13は感光性樹脂膜、23はポリシリコン層、
3は酸化膜、4は半導体基板である。この時のエツチン
グ中反応室内の圧力は1oPa程度である。しかしなが
ら、前記従来の方法では前記ポリシリコン層23のテー
パー形成に前記ポリシリコン層23の横方向エツチング
速度が前記ポリシリコン層23の縦方向エツチング速度
にほぼ等しいいわゆる等方性的エツチングの性質を利用
しているために1前記ポリシリコン層上の前記感光性樹
脂の所望するパターン幅が前記ポリシリコン層の膜厚の
約2倍以下程度になると、前記ポリシリコン層のエツチ
ング後の形状が第1図(a)の様な台形状にならず、′
XrJ1図(b)の様な三角形状になるという欠点があ
った。この図で14は感光性樹脂膜、24はポリシリコ
ン層である。In the same figure, 13 is a photosensitive resin film, 23 is a polysilicon layer,
3 is an oxide film, and 4 is a semiconductor substrate. At this time, the pressure inside the reaction chamber during etching is about 1oPa. However, in the conventional method, the so-called isotropic etching property in which the lateral etching speed of the polysilicon layer 23 is approximately equal to the vertical etching speed of the polysilicon layer 23 is used to form the taper of the polysilicon layer 23. 1. When the desired pattern width of the photosensitive resin on the polysilicon layer is approximately twice the thickness of the polysilicon layer or less, the shape of the polysilicon layer after etching becomes It does not become trapezoidal as shown in figure (a);
There was a drawback that it became triangular as shown in XrJ1 diagram (b). In this figure, 14 is a photosensitive resin film, and 24 is a polysilicon layer.
さらに、前記従来の方法によるポリシリコン層のテーパ
ーエッチでは、前記ポリシリコン層のオーバーエッチ量
によシ、前記ポリシリコン層のパターン幅が極端に変化
するため、前記ポリシリコン層のパターン幅を所望する
パターン幅に再現性良くエツチングすることが極めて困
難であるという欠点があった。Furthermore, in the taper etching of the polysilicon layer by the conventional method, the pattern width of the polysilicon layer changes drastically depending on the amount of overetching of the polysilicon layer. The disadvantage is that it is extremely difficult to perform etching with good reproducibility to a desired pattern width.
本発明は上述の従来の塩素系ガスあるいは弗素系ガスを
エツチングガスとして用いた反応性イオンエツチング、
または塩素系ガスあるいは弗素系ガスを用いた平行平板
プラズマエツチングによシポリシリコン層をチーパルエ
ツチングする方法の欠点を除去し、極めて信頼性の高い
多層配線構造を得ることの出来る前記ポリシリコン層の
テーパーエツチング方法を提供するものである。The present invention provides reactive ion etching using the above-mentioned conventional chlorine-based gas or fluorine-based gas as an etching gas;
Alternatively, the polysilicon layer can be etched by parallel plate plasma etching using chlorine gas or fluorine gas, thereby eliminating the drawbacks of the method of chipping the polysilicon layer and obtaining an extremely reliable multilayer wiring structure. The present invention provides a taper etching method.
本発明による方法は、半導体基板上に形成された酸化膜
等の絶縁膜上のポリシリコン層上に感光性樹脂膜を所望
するパターンに形成した後、前記感光性樹脂膜を矩形か
ら台形に断面形状を変化させるため、好ましくは140
℃〜180℃の温度のN2 プラズマ処理を行ない、
前記感光性樹脂膜を熱変形させ第2図(b)のよ5に台
形状にパターン形成し、塩素系ガスあるいは弗素系ガス
を用いた反応性イオンエツチングまたは、塩素系ガスあ
るいは弗素系ガスを用いた平行平板プラズマエッチング
により、前記台形状に形成された感光性樹脂膜をマスク
として、前記ポリシリコンと前記感光性樹脂膜とのエッ
チ速度比(選択比)が好ましくは2.0から5.0の範
囲内のエツチング条件で、前記ポリシリコン層をテーパ
ー状にエツチングする方法である。In the method according to the present invention, a photosensitive resin film is formed in a desired pattern on a polysilicon layer on an insulating film such as an oxide film formed on a semiconductor substrate, and then the cross section of the photosensitive resin film is changed from a rectangular shape to a trapezoidal shape. Preferably 140 to change the shape
Perform N2 plasma treatment at a temperature of ℃~180℃,
The photosensitive resin film is thermally deformed to form a trapezoidal pattern as shown in FIG. The etch rate ratio (selectivity) between the polysilicon and the photosensitive resin film is preferably 2.0 to 5.0 by using the parallel plate plasma etching process using the trapezoidal photosensitive resin film as a mask. In this method, the polysilicon layer is etched into a tapered shape under etching conditions within a range of 0.0.
次に図面を用いて本発明によるエツチング方法の一実施
例を示す。Next, an embodiment of the etching method according to the present invention will be described with reference to the drawings.
第2図(a)において用いる半導体4例えばN型シリコ
ンウェハーの表面上に絶縁膜3として例えば酸化膜を形
成した後に、前記絶i[3上にポリシリコン層2例えば
リンドープされたポリシリコン層を約600 oA 形
成する。その後このポリシリコン層上にポジタイプ感光
性樹脂lftX1例えば0FPR−800(東京応化社
の製品名)を所望するパターンに形成し、N2雰囲気中
で30分間ボストベークを行なう。この時の温度は約1
00 ’Oから130°0の範囲内のある温度に設定し
、±5°Cの精度で温度制御する。After forming, for example, an oxide film as an insulating film 3 on the surface of a semiconductor 4, for example, an N-type silicon wafer used in FIG. Approximately 600 oA is formed. Thereafter, a positive type photosensitive resin lftX1, for example, 0FPR-800 (product name of Tokyo Ohka Co., Ltd.) is formed in a desired pattern on this polysilicon layer, and post-baked for 30 minutes in an N2 atmosphere. The temperature at this time is approximately 1
The temperature is set within the range from 00'O to 130°0, and the temperature is controlled with an accuracy of ±5°C.
次にN2ガスを使用したバレル型プラズマエツチング装
蓋によシ、第2図(a)の様に上述した方法で前記感光
性樹脂膜をバターニングした半導体ウェハーを140°
0から180℃の任意の温度でN2ブ2ズマ処理を30
分程度行ない前記感光性樹脂膜1(第1図(a))を第
2図(b)の11の様に断面形状を台形状に熱変形させ
る。この時のN2プラズマ処理条件は例えば、励起周波
数が13.56MHz 。Next, the semiconductor wafer with the photosensitive resin film patterned by the method described above is placed in a barrel-type plasma etching cap using N2 gas at a 140° angle, as shown in FIG. 2(a).
N2 bubble treatment at any temperature from 0 to 180℃ for 30 minutes.
The photosensitive resin film 1 (FIG. 1(a)) is thermally deformed into a trapezoidal cross-sectional shape as indicated by 11 in FIG. 2(b). The N2 plasma processing conditions at this time are, for example, an excitation frequency of 13.56 MHz.
反応室内のプラズマ処理中圧力は0.4〜0.6Tor
r。The pressure during plasma treatment in the reaction chamber is 0.4 to 0.6 Torr.
r.
几、F、パワーが200Wである。Rin, F, power is 200W.
ここでN2プラズマ処理の温度が高いほど、前記感光性
樹脂膜の前記ポリシリコン層との接触角は鋭角になる。Here, the higher the temperature of the N2 plasma treatment, the more acute the contact angle between the photosensitive resin film and the polysilicon layer.
次に塩素系ガスあるいは弗素系ガス例えばCCt2F、
にN2を添加したガスをエツチングガスとして使用する
反応性イオンエツチングによシ、前記感光性樹脂膜11
をマスクに前記ポリシリコン層2をエツチングする。こ
の時のエツチング条件は例えば励起周波数を13.56
MHz、几、F、パワーが600W、CC2,F2流景
が60CC/min。Next, chlorine-based gas or fluorine-based gas such as CCt2F,
The photosensitive resin film 11 is etched by reactive ion etching using a gas containing N2 added to the etching gas as an etching gas.
The polysilicon layer 2 is etched using the mask as a mask. The etching conditions at this time are, for example, an excitation frequency of 13.56.
MHz, 几, F, power is 600W, CC2, F2 stream view is 60CC/min.
N2流景が15 CC/min、エツチング中の反応室
内の圧力が16Paである。The N2 flow rate was 15 CC/min, and the pressure inside the reaction chamber during etching was 16 Pa.
エツチングが進行し、前記感光性樹脂膜11が、前記ポ
リシリコン膜21との界面A点で残っている時は、前記
ポリシリコン膜2′にアンダーカットはない(第2図C
)。When the etching progresses and the photosensitive resin film 11 remains at the interface point A with the polysilicon film 21, there is no undercut in the polysilicon film 2' (FIG. 2C).
).
さらにエツチングが進行すると前記感光樹脂膜12がエ
ツチング中に損耗し、A点から内側に後退し、第2図(
d)の12の様になる。この時、感光性樹脂膜12がエ
ツチングによシ後退するとともにポリシリコン膜21が
テーパー状にエツチングされ始め、エツチングが終了す
ると第2図(d)に示す様にポリシリコン層22の様に
テーパー状になる。したがって、感光性樹脂膜のポリシ
リコン層との接触角が鋭い程ポリシリコン層のテーパー
の角度は鋭くなる。さらに、前記感光性樹脂膜11(第
2図(C))がA点より内側へ後退する速さは前記選択
比が小さい程速くなることから、前記ポリシリコン層の
テーパーの角度は前記選択比にも依存するが、本発明で
は前記選択比は一定となるエツチング条件で、N2プラ
ズマ処理の温度条件を変えることによシ、前記ポリシリ
コン層のテーパーの角度を任意に変える方法でテーパー
エッチを行なう。As the etching progresses further, the photosensitive resin film 12 is worn away during etching and retreats inward from point A, as shown in FIG.
It will look like d) 12. At this time, as the photosensitive resin film 12 retreats due to etching, the polysilicon film 21 begins to be etched into a tapered shape, and when the etching is completed, the polysilicon layer 22 becomes tapered as shown in FIG. 2(d). It becomes like this. Therefore, the sharper the contact angle of the photosensitive resin film with the polysilicon layer, the sharper the taper angle of the polysilicon layer. Further, since the speed at which the photosensitive resin film 11 (FIG. 2(C)) retreats inward from point A increases as the selectivity ratio decreases, the taper angle of the polysilicon layer is determined by the selectivity ratio. However, in the present invention, taper etching is performed by changing the taper angle of the polysilicon layer arbitrarily by changing the temperature conditions of the N2 plasma treatment under etching conditions that keep the selectivity constant. Let's do it.
以上述べた如く、本発明によると塩素系ガスあるいは弗
素系ガスを使用した反応性イオンエツチングまたは、塩
素系ガスあるいは弗素系ガスを使用した平行平板プラズ
マエッ°チングによシ、半導体基板上の酸化膜等の絶縁
膜上のポリシリコン層上に所望のパターンとして形成し
た感光性樹脂膜をマスクに、前記ポリシリコン層をテー
パーエッチする方法において、従来の方法と比較して前
記ポリシリコン層のパターン幅が微細なパターン(1,
5μm程度)までテーパーエッチが可能なこと、および
前記ポリシリコン層のテーパー角度が任意に制御できる
という利点が明らかになった。As described above, according to the present invention, reactive ion etching using chlorine-based gas or fluorine-based gas or parallel plate plasma etching using chlorine-based gas or fluorine-based gas is performed to oxidize a semiconductor substrate. In a method of taper etching the polysilicon layer using a photosensitive resin film formed in a desired pattern on a polysilicon layer on an insulating film such as a film as a mask, the pattern of the polysilicon layer is Pattern with fine width (1,
It has become clear that taper etching is possible up to a thickness of about 5 μm) and that the taper angle of the polysilicon layer can be controlled arbitrarily.
したがって本発明によるテーパーエッチ方法は、極めて
信頼性の高い多層配線構造を得ることのできる制御性の
高いテーパーエッチ方法であることが明らかである。Therefore, it is clear that the taper etching method according to the present invention is a highly controllable taper etching method that can obtain an extremely reliable multilayer wiring structure.
第1図(a)乃至第1図(b)は従来のエツチング方法
によシポリシリコン層をテーパーエツチングしだ後のポ
リシリコン層のテーパー形状を示す断面図である。
第1図(a)はマスクとして使用する感光性樹脂膜のパ
ターン幅がエツチングされるポリシリコン層の膜厚の2
倍よシ充分に大きい場合の断面図を示すO
第1図(b)はマスクとして使用する感光性樹脂膜のパ
ターン幅がエツチングされるポリシリコン層の膜厚の約
2倍程度の場合の断面図を示す。
第2図(a)乃至第2図(d)は本発明の実施例の各工
程を説明するための断面図である。
なお、図において、
1.11,12,13,14・・・・・・感光性樹脂膜
、2.21,22,23.24・・・・・・ポリシリコ
ン層、3・・・・・・絶縁膜例えば酸化膜、4・・・・
・・半尋体基板例えばN型シリコンウェハー、破ma・
・・・・・N2プラズマ処理する前の感光性at脂膜1
の型、破i!′!i!b・・・・・・エツチング中の感
光性樹脂ノlrJが後退する前の型、である。FIGS. 1(a) and 1(b) are cross-sectional views showing the tapered shape of the polysilicon layer after the polysilicon layer has been tapered by a conventional etching method. Figure 1(a) shows that the pattern width of the photosensitive resin film used as a mask is 2 times the film thickness of the polysilicon layer to be etched.
Figure 1 (b) shows a cross section when the pattern width of the photosensitive resin film used as a mask is about twice the thickness of the polysilicon layer to be etched. Show the diagram. FIGS. 2(a) to 2(d) are cross-sectional views for explaining each process of an embodiment of the present invention. In the figure, 1.11, 12, 13, 14... photosensitive resin film, 2.21, 22, 23.24... polysilicon layer, 3...・Insulating film, e.g. oxide film, 4...
・Semiconductor substrate e.g. N-type silicon wafer, broken ma.
...Photosensitive at oil film 1 before N2 plasma treatment
Breaking the mold! ′! i! b... This is the mold before the photosensitive resin lrJ recedes during etching.
Claims (3)
イオンエッチング、または前記ガスを使用した平行平板
プラズマエッチングにより、半導体基板上に形成された
ポリシリコン層を、前記ポリシリコン層上に所望のパタ
ーンとして形成した感光性樹脂膜をマスクに、前記ポリ
シリコン層をテーパーエッチする方法において、断面形
状が矩形である前記感光性樹脂膜にプラズマ処理を加え
、前記感光性樹脂膜を台形状に熱変形させ、前記台形状
感光性樹脂膜をマスクとして、前記ポリシリコン層をエ
ッチングすることにより、前記ポリシリコン層にテーパ
ーを形成することを特徴とする半導体装置の製造方法。(1) A polysilicon layer formed on a semiconductor substrate is formed on the polysilicon layer by reactive ion etching using chlorine-based gas or fluorine-based gas, or parallel plate plasma etching using the above gas. In the method of taper etching the polysilicon layer using a photosensitive resin film formed as a pattern as a mask, plasma treatment is applied to the photosensitive resin film having a rectangular cross section, and the photosensitive resin film is heated into a trapezoidal shape. A method for manufacturing a semiconductor device, comprising forming a taper in the polysilicon layer by deforming the polysilicon layer and etching the polysilicon layer using the trapezoidal photosensitive resin film as a mask.
0℃から180℃の温度であり、かつプラズマ処理は窒
素(N_2)プラズマ処理であることを特徴とする特許
請求の範囲第(1)項記載の半導体装置の製造方法。(2) The conditions for applying plasma treatment to the photosensitive resin film are 14
The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is from 0° C. to 180° C. and the plasma treatment is nitrogen (N_2) plasma treatment.
と前記感光性樹脂膜のエッチング速度比が2.0から5
.0の範囲内のエッチング条件で行うことを特徴とする
特許請求の範囲第(1)項もしくは第(2)項記載の半
導体装置の製造方法。(3) When etching the polysilicon layer, the etching rate ratio between the polysilicon and the photosensitive resin film is 2.0 to 5.
.. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is performed under etching conditions within a range of 0.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18390484A JPS6161424A (en) | 1984-09-03 | 1984-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18390484A JPS6161424A (en) | 1984-09-03 | 1984-09-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6161424A true JPS6161424A (en) | 1986-03-29 |
Family
ID=16143846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18390484A Pending JPS6161424A (en) | 1984-09-03 | 1984-09-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6161424A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61144026A (en) * | 1984-12-17 | 1986-07-01 | Toshiba Corp | Dry etching method |
JPS63240639A (en) * | 1987-03-27 | 1988-10-06 | Nec Corp | Microcomputer |
US5316616A (en) * | 1988-02-09 | 1994-05-31 | Fujitsu Limited | Dry etching with hydrogen bromide or bromine |
CN105336602A (en) * | 2014-07-15 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method of making polycrystalline silicon etch sidewall angle |
-
1984
- 1984-09-03 JP JP18390484A patent/JPS6161424A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61144026A (en) * | 1984-12-17 | 1986-07-01 | Toshiba Corp | Dry etching method |
JPS63240639A (en) * | 1987-03-27 | 1988-10-06 | Nec Corp | Microcomputer |
US5316616A (en) * | 1988-02-09 | 1994-05-31 | Fujitsu Limited | Dry etching with hydrogen bromide or bromine |
CN105336602A (en) * | 2014-07-15 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method of making polycrystalline silicon etch sidewall angle |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1155973A (en) | Method of etching | |
US5160407A (en) | Low pressure anisotropic etch process for tantalum silicide or titanium silicide layer formed over polysilicon layer deposited on silicon oxide layer on semiconductor wafer | |
JPS62291940A (en) | Manufacture of semiconductor device | |
JPS6161424A (en) | Manufacture of semiconductor device | |
US5338703A (en) | Method for producing a recessed gate field effect transistor | |
JPH0114698B2 (en) | ||
JPH07326621A (en) | Minute pattern forming method for semiconductor element | |
JPH07135247A (en) | Manufacture of semiconductor device | |
JP3371988B2 (en) | Processing method of thin film | |
US7005385B2 (en) | Method for removing a resist mask with high selectivity to a carbon hard mask used for semiconductor structuring | |
KR100466192B1 (en) | Method for manufacturing semiconductor device | |
KR100228275B1 (en) | Method for fabricating semiconductor device | |
JPH11311579A (en) | Method for forming diaphragm of semiconductor pressure sensor | |
JPH0198229A (en) | Manufacture of semiconductor device | |
KR100186250B1 (en) | Method of manufacturing field emission device of fed | |
JPS6290934A (en) | Flattening etching method | |
KR20030038651A (en) | Process for selectively etching doped silicon dioxide over undoped silicon dioxide and silicon nitride | |
KR19990081061A (en) | Method of forming fine contact hole in semiconductor device | |
JPH0430518A (en) | Manufacture of semiconductor device | |
JPH0497523A (en) | Manufacture of semiconductor device | |
JPS61296722A (en) | Manufacture of semiconductor device | |
JPS59228722A (en) | Method of forming minute electrode wiring | |
KR0141965B1 (en) | Slant etching method of metal layer | |
JPH027521A (en) | Manufacture of semiconductor device | |
JPS60149136A (en) | Manufacture of semiconductor device |