JPS62291940A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62291940A
JPS62291940A JP61136531A JP13653186A JPS62291940A JP S62291940 A JPS62291940 A JP S62291940A JP 61136531 A JP61136531 A JP 61136531A JP 13653186 A JP13653186 A JP 13653186A JP S62291940 A JPS62291940 A JP S62291940A
Authority
JP
Japan
Prior art keywords
film
etching
oxidation
resistant
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61136531A
Other languages
Japanese (ja)
Other versions
JPH0779133B2 (en
Inventor
Norihiko Tamaoki
徳彦 玉置
Masabumi Kubota
正文 久保田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61136531A priority Critical patent/JPH0779133B2/en
Publication of JPS62291940A publication Critical patent/JPS62291940A/en
Priority to US07/268,604 priority patent/US4845048A/en
Publication of JPH0779133B2 publication Critical patent/JPH0779133B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

Abstract

PURPOSE:To provide a narrow separating groove by separating an etching resistant film and an oxidation resistant film to uniformly isotropically etch the films by dry etching. CONSTITUTION:A thermal oxide film 2, an Si3N4 film 3 and an SiO2 film 4 are superposed on an N-type Si substrate 1, and etched by RIE to open a hole 5. It is covered with the film 2, a CVD Si3N4 film 7 is superposed, etched by RIE, and the film 7 remains on the sidewall. The whole surface is again covered with an SiO2 film 8, etched by RIE, and remains only on the sidewall. With the films 4, 8 as masks it is isotropically etched by microwave discharge with CF4+O2. Then, even a gap of the film 8 of 0.2um or thinner can be preferably etched to obtain a narrow element separating groove. Then, it is oxidized under high pressure to insulate and separate an element region 10 of the substrate 1 by an oxide film 11 from the substrate.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 産業上の利用分野 本発明は高密度・高速・低消費電力性を備えた半導体装
置の製造方法に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device with high density, high speed, and low power consumption.

従来の技術 半導体集積回路においては高密度・高速化・低消費電力
化が追い求められており、素子間の分離領域の低減によ
る高密度化やＭＯ３素子におけるソース・ドレインと基
板間に発生する寄生容量などの低減による高速・低消費
電力化などを狙ってＳ　ＯＩ　（５ｉｌｉｃｏｎ　Ｏｎ
　Ｉｎ５ｕ１２Ｌｔｏｒ　）構造の素子の開発において
さまざまな試みが実施されている。Conventional technology In semiconductor integrated circuits, high density, high speed, and low power consumption are being sought after. SOI (5ilicon On
Various attempts have been made in developing devices with In5u12Ltor) structure.

第２図は特開昭５４−８８８７１号公報に示されている
溝堀り分離発展型のＳＯＩ構造半導体装置の製造工程の
一例を示す断面図である。FIG. 2 is a sectional view showing an example of the manufacturing process of a trench isolation development type SOI structure semiconductor device disclosed in Japanese Unexamined Patent Publication No. 54-88871.

まず第２図ａのように、シリコン基板１の上に選択的に
開口された５ｉ５Ｎ４膜２を形成する。次にｂに示すよ
うに、　Ｓｉ　５Ｎ　４膜２をマスクとして、異方性の
強いドライエッチ法、たとえば反応性イオンエッチ（Ｒ
，ＩＪ）でシリコン基板１に開口部３を形成する。この
急峻な開口面に対し第２図ｇのように、５ｉ５Ｎ４膜４
を減圧ＣＶＤ法によって付着させる。次にｄに示すよう
に、スパッタエツチング法によりＳｉ３Ｎ４　膜４を除
去する。スパッタエツチング法は、エツチングの直線性
が優れているため、側面の　Ｓｉ　５Ｎ　４膜４はエツ
チングされず、第２図ｄのように５ｉ５Ｎ４膜２の上面
部及びシリコン基板開口部３底面のみがエツチングされ
る。その後、第２図ｅのようにシリコン基板１のエツチ
ングを行ない、第２図ｆに示すように酸化を実施し、酸
化物領域６を形成すると単結晶シリコン島領域６の下面
全域が両側からの酸化によりつながる。その後、単結晶
シリコン島領域６表面のＳｉ３Ｎ４膜を除去すると、第
２図ｇに示すように単結晶シリコン島領域６の下面およ
び側面全てが酸化物領域６により囲まれた構造となる。First, as shown in FIG. 2a, a 5i5N4 film 2 with selective openings is formed on a silicon substrate 1. Next, as shown in b, using the Si 5N 4 film 2 as a mask, a highly anisotropic dry etching method such as reactive ion etching (R
, IJ) to form an opening 3 in the silicon substrate 1. As shown in Figure 2g, the 5i5N4 film 4
is deposited by low pressure CVD method. Next, as shown in d, the Si3N4 film 4 is removed by sputter etching. Since the sputter etching method has excellent etching linearity, the Si 5N 4 film 4 on the side surface is not etched, but only the top surface of the 5i 5N 4 film 2 and the bottom surface of the silicon substrate opening 3 are etched, as shown in FIG. be done. Thereafter, the silicon substrate 1 is etched as shown in FIG. 2e, and oxidized as shown in FIG. Connected by oxidation. Thereafter, when the Si3N4 film on the surface of the single-crystal silicon island region 6 is removed, a structure is formed in which the entire bottom and side surfaces of the single-crystal silicon island region 6 are surrounded by the oxide region 6, as shown in FIG. 2g.

発明が解決しようとする問題点 ここで第２図ｅで示したシリコン基板のエツチングは、
次の（第２図ｆ）酸化工程によるシリコン島領域の形状
安定化や、酸化時間の短縮化によるシリコン島領域内の
欠陥の低減化という点から等方向なエツチングにする必
要がある。同様な溝堀り分離発展型のＳＯＩ構造半導体
装置の製造方法（特開昭６８−２５０４２９　）ではこ
の等方向なエツチングをたとえば湿式のエツチングで行
なうように記している。Problems to be Solved by the Invention The etching of the silicon substrate shown in FIG. 2e is as follows.
It is necessary to perform isodirectional etching in order to stabilize the shape of the silicon island region by the next oxidation step (FIG. 2f) and to reduce defects in the silicon island region by shortening the oxidation time. A similar method for manufacturing a SOI structure semiconductor device using trench isolation and development (Japanese Patent Application Laid-Open No. 68-250429) describes that this isodirectional etching is performed by, for example, wet etching.

しかしながら、湿式エツチングでは高密度化に伴ない、
隣合うシリコン高量の分離領域が狭まるにつれて、液が
入り込みにくくなり、エツチング形状にバラツキがおこ
りシリコン島底部が酸化されたりされなかったりという
問題点が起ってくる。However, with wet etching, as the density increases,
As adjacent silicon-rich isolation regions become narrower, it becomes difficult for liquid to penetrate, leading to variations in the etching shape and problems such as oxidation of the bottom of the silicon island or failure to oxidize.

この現象はＳＦ６ガス等を用いた等方性の強いプラズマ
エツチングでも見られ、シリコン高量の分離領域の幅が
狭まるにつれ、エツチングが進みにくくなってしまう。This phenomenon is also observed in highly isotropic plasma etching using SF6 gas, etc., and as the width of the silicon-rich isolation region becomes narrower, etching becomes more difficult to proceed.

問題点を解決するだめの手段 上記問題点を解決するため、本発明ではＣＦ４゜０２等
のガスを用いたマイクロ波放電によるエツチングをこの
等方性工・ソチング工程に適用した。Means for Solving the Problems In order to solve the above problems, in the present invention, etching by microwave discharge using a gas such as CF4.02 is applied to this isotropic processing/soching process.

反応性ラジカルのみがエツチングに関与するので０．２
μｍ以下のシリコン高量の分離領域においてもエツチン
グが等方向にかつ、深さ方向についても広い分離領域と
同等に進む。また、ＳＦ６　ガスを用いたプラズマエっ
チング等でも同様なことが言えるのであるが、このマイ
クロ波放電によるエツチングでは耐酸化性被膜としてシ
リコン窒化膜を使用したときシリコンとシリコン窒化膜
の選択比は十分ではないが、次の酸化工程での耐酸化性
被膜としてのシリコン窒化膜をシリコン島上面及び側面
とも例えばシリコン酸化膜等の耐エツチングマスクで被
層することによりこれを解決した。0.2 since only reactive radicals are involved in etching.
Etching progresses in the same direction even in a silicon-rich isolation region of less than .mu.m, and in the same manner as in a wide isolation region in the depth direction. The same thing can be said about plasma etching using SF6 gas, but when using silicon nitride as the oxidation-resistant film, the selectivity between silicon and silicon nitride is sufficient in this microwave discharge etching. However, this problem was solved by covering both the top and side surfaces of the silicon island with a silicon nitride film as an oxidation-resistant film in the next oxidation step using an etching-resistant mask such as a silicon oxide film.

作用 上記手段に示すように耐エツチング性被膜と耐酸化性被
膜とを分離することにより、ドライエツチングを用いて
等方向なエツチングを均一性よく行なうことが可能にな
った。Effect: By separating the etching-resistant film and the oxidation-resistant film as shown in the above means, it has become possible to perform isodirectional etching with good uniformity using dry etching.

実施例 第１図は本発明の一実施例における半導体装置の製造工
程を示す断面図である。Embodiment FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device in an embodiment of the present invention.

第１図において、１はｎ型（１００）シリコン基板で比
抵抗は０．６〜１、ＯΩαである。２は膜厚１０００人
のシリコン熱酸化膜、３は耐酸化性被膜としての膜厚２
０００人のシリコン窒化膜、４は異方性及び等方性の２
度のドライエツチング工程における耐ドライエツチマス
クとしての膜厚３０００人のシリコン酸化膜である。６
は異方性工、７チングにより、シリコン基板に形成され
た開口部、６は膜厚５００人のシリコン熱酸化膜、７は
膜厚１０００人のシリコン窒化膜、８は膜厚１０００人
のシリコン酸化膜、９は等方性ドライエツチングにより
シリコン基板に形成された開口部、１ｏはシリコン基板
から絶縁分離された素子領域、１１は酸化膜領域である
。In FIG. 1, 1 is an n-type (100) silicon substrate with a specific resistance of 0.6 to 1, OΩα. 2 is a silicon thermal oxide film with a thickness of 1000, and 3 is a film thickness of 2 as an oxidation-resistant film.
000 silicon nitride film, 4 is anisotropic and isotropic 2
This is a silicon oxide film with a thickness of 3,000 yen as a dry etching resistant mask in the dry etching process. 6
7 is an opening formed in a silicon substrate by anisotropic etching, 6 is a silicon thermal oxide film with a thickness of 500 μm, 7 is a silicon nitride film with a thickness of 1000 μm, and 8 is a silicon film with a thickness of 1000 μm. An oxide film, 9 is an opening formed in a silicon substrate by isotropic dry etching, 1o is an element region insulated and isolated from the silicon substrate, and 11 is an oxide film region.

まず、第１図ａのようにｎ型基板１上に熱酸化膜２・シ
リコン窒化膜３・シリコン酸化膜４を順に形成し、素子
領域となる部分以外（分離領域）を異方性の強い反応性
イオンエツチング（Ｒ，ＩＪ）等を用いて開口する。次
に第１図すに示すように分離領域となる部分をこれもＲ
，ＩＪ　　等を用いてシリコン酸化膜４をマスクとして
エツチングし、開口部６を形成する。このときシリコン
酸化膜４の膜厚は減少するが後の熱酸化膜、シリコン窒
化膜の異方性エツチングの下地及びシリコン基板の等方
性ドライエツチングのエツチングマスクとして使用でき
る膜厚（１６００Å以上）は残っている。次に第１図Ｃ
のように、シリコン窒化膜３をマスクとして熱酸化を行
ない、開口部の側面及び底面に熱酸化膜６を形成し、そ
の後全面にシリコン窒化膜７を減圧ｃｖｎ法等で形成す
る。なお、この減圧ＣＶＤ法は開口部６の側面へもシリ
コン窒化膜７を均質に付着されるために用いている。First, as shown in FIG. Openings are made using reactive ion etching (R, IJ) or the like. Next, as shown in Figure 1, the part that will become the separation area is also rounded.
, IJ, etc., using the silicon oxide film 4 as a mask to form an opening 6. At this time, the film thickness of the silicon oxide film 4 decreases, but the film thickness is such that it can be used as a base for later anisotropic etching of the thermal oxide film and silicon nitride film, and as an etching mask for isotropic dry etching of the silicon substrate (1600 Å or more). remains. Next, Figure 1C
As shown, thermal oxidation is performed using the silicon nitride film 3 as a mask to form a thermal oxide film 6 on the side and bottom surfaces of the opening, and then a silicon nitride film 7 is formed on the entire surface by low pressure CVN method or the like. Note that this low pressure CVD method is used to uniformly deposit the silicon nitride film 7 on the side surfaces of the opening 6 as well.

この後、第１図ｄのように、反応性イオンエツチング法
で異方性の強いエツチングを行なうと、開口部らの側壁
部のシリコン熱酸化膜６．シリコン窒化膜７のみを残し
てその他のシリコン酸化膜・窒化膜が除去される。ここ
でもシリコン酸化膜４の膜厚は減少するが、後のシリコ
ン基板の等方性ドライエツチング工程でのエツチングマ
スクとして使用できる膜厚（６００Å以上）は残されて
いる。次に等方性ドライエツチング工程でのマスク材と
してのシリコン酸化膜を開口部側面のシリコン窒化膜７
上に被覆させた形で残すために、前のシリコン窒化膜７
で行なったのと同様に減圧ＣＶＤ法等で全面にシリコン
酸化膜８を形成しく第１図ｅ）、反応性イオンエツチン
グ法で側壁部のみを残し、その他のシリコン酸化膜８を
除去する（第１図ｆ）。次にシリコン酸化膜４及び８を
マスクトシて　ＣＦ４・　ｏ２ガスを用いたマイクロ波
放電等によるシリコン基板の等方性エツチングを行ない
開口部９を形成する（第１図ｇ）。マイクロ波放電を用
いたエツチングは他のドライエッチ法に比べてシリコン
基板とシリコン酸化膜との選択性が非常に良好（８１／
３１０２選択比２０以上）であるためエツチングマスク
としてのシリコン酸化膜８の膜厚が薄くてすみ、また隣
合った素子領域側面のシリコン酸化膜８間の距離が０．
２μｍ以下であっても、他の分離領域が広い部分と同様
に等方性エツチングが進むため、分離領域幅を１　μｍ
以下に狭めることができ、均一性の良い素子形状を保ち
ながら高密度に素子を形成することができる。Thereafter, as shown in FIG. 1d, when highly anisotropic etching is performed using a reactive ion etching method, the silicon thermal oxide film 6. The other silicon oxide and nitride films are removed, leaving only the silicon nitride film 7. Although the film thickness of the silicon oxide film 4 is reduced here as well, there remains a film thickness (600 Å or more) that can be used as an etching mask in the subsequent isotropic dry etching process of the silicon substrate. Next, the silicon oxide film used as a mask material in the isotropic dry etching process is replaced with a silicon nitride film 7 on the side surface of the opening.
The previous silicon nitride film 7 is left coated on top.
A silicon oxide film 8 is formed on the entire surface by low-pressure CVD, etc., in the same way as was done in Figure 1e), and the rest of the silicon oxide film 8 is removed by reactive ion etching, leaving only the sidewalls (Fig. 1e). Figure 1 f). Next, the silicon oxide films 4 and 8 are masked and the silicon substrate is isotropically etched by microwave discharge using CF4.O2 gas to form an opening 9 (FIG. 1g). Etching using microwave discharge has very good selectivity between the silicon substrate and silicon oxide film compared to other dry etching methods (81/
3102 selectivity of 20 or more), the thickness of the silicon oxide film 8 serving as an etching mask can be made thin, and the distance between the silicon oxide films 8 on the sides of adjacent element regions is 0.
Even if the width of the separation region is less than 2 μm, isotropic etching will proceed in the same way as other wide separation regions, so the width of the separation region should be set to 1 μm.
It is possible to form elements with high density while maintaining a uniform element shape.

また　ＳＦ６ガスを用いたプラズマエツチング等を使用
する場合でも選択性を向上させるという点においてはあ
る程度の効果を得られる。この後第１図りに示すように
、高圧酸化法により約７気圧の圧力下で酸化を行なうと
、酸化される領域はシリコン窒化膜３．７に覆われてい
ない領域に限定されるため、開口部深さ・酸化時間・素
子領域幅を最適化するとシリコン基板１の一部からなる
素子領域１ｏが酸化膜領域１１によりシリコン基板と分
離・絶縁された構造を得ることができる。Further, even when plasma etching using SF6 gas is used, a certain degree of effect can be obtained in terms of improving selectivity. After this, as shown in the first diagram, when oxidation is carried out under a pressure of about 7 atmospheres using the high-pressure oxidation method, the area to be oxidized is limited to the area not covered with the silicon nitride film 3.7, so the opening By optimizing the depth, oxidation time, and device region width, it is possible to obtain a structure in which the device region 1o, which is a part of the silicon substrate 1, is separated and insulated from the silicon substrate by the oxide film region 11.

以下、この後の工程については省略するが、既知の方法
により分離領域をシリコン酸化膜・ポリシリコン等で埋
め込み、ＭＯＳデバイスなどを形成する。Although subsequent steps will be omitted below, the isolation region is filled with a silicon oxide film, polysilicon, etc. by a known method to form a MOS device or the like.

発明の詳細 な説明した発明によれば、溝堀り分離発展型ＳＯＩ構造
素子の製造技術において耐エツチング性マスク材と耐酸
化性被膜を分離することにより、工業性に優れ均一性が
良好なドライエツチング技術を用い、素子間の分離領域
を１　μｍ以下に抑えることが可能になった。パターン
寸法が１μｍをきる今後の半導体集積回路製造技術の中
で高速・低消費電力なＳＯＩ構造素子を高密度に形成す
るための極めて工業的価値の高いものである。According to the invention described in detail, by separating the etching-resistant mask material and the oxidation-resistant film in the manufacturing technology of the groove-separated developed SOI structure element, a dry film with excellent industrial efficiency and good uniformity can be obtained. Using etching technology, it has become possible to suppress the isolation region between elements to 1 μm or less. It is of extremely high industrial value for forming high-speed, low-power consumption SOI structural elements at high density in future semiconductor integrated circuit manufacturing technology where pattern dimensions are less than 1 μm.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例における半導体装置の製造方
法を示す工程断面図、第２図は従来の溝堀り分離発展型
ＳＯＩ構造素子の製造方法を示す工程断面図である。 ３．７・・・・・・シリコン窒化！、４．８・・・・・
・シリコン酸化膜、６・・・・・・開口部、１０・・・
・・・素子領域、１１・・・・・・シリコン熱酸化膜。 代理人の氏名　弁理士　中　尾　敏　男　はが１名第１
図 第１図FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a trench isolation development type SOI structure element. 3.7...Silicon nitriding! , 4.8...
・Silicon oxide film, 6...opening, 10...
. . . Element region, 11 . . . Silicon thermal oxide film. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 1

Claims (5)

【特許請求の範囲】[Claims] （１）半導体基板に形成された第１の耐エッチング性マ
スク材と耐酸化性被膜をマスクとして前記半導体基板に
開口部を形成する工程と、第２の耐エッチング性マスク
材と耐酸化性被膜を減圧ＣＶＤ法と異方性エッチングに
より前記開口部側面に形成させる工程と、前記第１およ
び第２の耐エッチング性マスク材をマスクとして等方性
ドライエッチングを行なう工程と、前記第１および第２
の耐酸化被膜をマスクとして酸化性雰囲気中で熱処理を
行なう工程とを含む半導体装置の製造方法。(1) A step of forming an opening in the semiconductor substrate using a first etching-resistant mask material and an oxidation-resistant coating formed on a semiconductor substrate as a mask, and a second etching-resistant masking material and an oxidation-resistant coating formed on a semiconductor substrate. forming on the side surface of the opening by low pressure CVD and anisotropic etching; performing isotropic dry etching using the first and second etching-resistant mask materials as masks; 2
A method for manufacturing a semiconductor device, the method comprising: performing heat treatment in an oxidizing atmosphere using the oxidation-resistant film as a mask. （２）等方性ドライエッチ工程においてＣＦ＿４、Ｏ＿
２ガスを用いたマイクロ波放電によるドライエッチング
を行なう特許請求の範囲第１項記載の半導体装置の製造
方法。(2) CF_4, O_ in the isotropic dry etching process
2. The method of manufacturing a semiconductor device according to claim 1, wherein dry etching is performed by microwave discharge using two gases. （３）第１及び第２の耐エッチングマスク材にシリコン
酸化膜を用いる特許請求の範囲第１項記載の半導体装置
の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein silicon oxide films are used as the first and second etching-resistant mask materials. （４）酸化工程において１１００℃以上の高温における
酸化を行ない酸化膜と半導体基板との応力を緩和し欠陥
を低減する特許請求の範囲第１項記載の半導体装置の製
造方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein in the oxidation step, oxidation is performed at a high temperature of 1100° C. or higher to relieve stress between the oxide film and the semiconductor substrate and reduce defects. （５）第１及び第２の耐酸化性被膜としてシリコン窒化
膜を用いる特許請求の範囲第１項記載の半導体装置の製
造方法。(5) The method of manufacturing a semiconductor device according to claim 1, wherein silicon nitride films are used as the first and second oxidation-resistant films.
JP61136531A 1986-06-12 1986-06-12 Method for manufacturing semiconductor device Expired - Lifetime JPH0779133B2 (en)

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JP61136531A JPH0779133B2 (en) 1986-06-12 1986-06-12 Method for manufacturing semiconductor device
US07/268,604 US4845048A (en) 1986-06-12 1988-11-07 Method of fabricating semiconductor device

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JPH0779133B2 JPH0779133B2 (en) 1995-08-23

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US4845048A (en) 1989-07-04

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