JPS61287233A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an ultrafine groove with good reproducibility by allowing a burying material (polysilicon) on the side wall of a pattern by an etching-back technique to remain, and then etching the material and an Si substrate disposed under the material. CONSTITUTION:An Si3N4 film 22 and an SiO2 film 23 having an ultrafine window are superposed on an Si substrate 21, and coated with a polysilicon 24. A polysilicon 25 is retained on the wide wall of the window by RIE. Then, an SiO2 film 26 is superposed, etched back, an SiO2 film 27 is retained at the center of the window to expose the polysilicon 25. With the films 27, 23 as masks the polysilicon 25 and the film 22 directly under the polysilicon 25 are etched. Subsequently, the substrate 21 is subjected to an RIE to form a groove 28. Thereafter, the insulating films 22, 23, 27 are etched to form a gate oxide film 29 and a gate electrode 30. Then, an ultrafine capacitor is obtained. This structure may be used widely for an element separation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a groove in a semiconductor substrate.

[Technical fishing of invention m]

It is well known to form trenches in a silicon substrate to create gap capacitors for dynamic memories.

Various proposals have already been made regarding the shape of the groove and its formation method, but the one closest to the present invention (for example, as a prior art,
1984 Conference on Solid Stay
~Device Ant Materials (Confere)
nce on 5solidState Devices
Ultra Sharp Trench Capacitors Formed by Peripheral Etching (Ultra Sharp Trench Capacitors Formed by Peripheral Etching)
5harp Trench Capacitors F
ormed by Peripheral Etchin
g). This technique will be explained below with reference to FIG. 3 of the accompanying drawings.

FIGS. 3(a) to 3(d) are cross-sectional views of each step for explaining a groove forming method according to the prior art. As shown in FIG. 3(a), an oxide film 12 and a molybdenum silicide film (MoSi2) 13 are formed on a silicon substrate 11. Then, a photoresist 14 is formed on the surface in a predetermined shape, for example, a rectangle of about 1 μm×1 μm.

Next, this substrate 11 is subjected to RI E (Reactive Ion [tch
ing) method. At this time, 02 and C
If the a degree of Cl4 is properly set, only the MoSi2 film 13 in the peripheral area 15 of the resist 14 can be etched, and a structure as shown in FIG. 3(b) can be obtained. This utilizes the fact that the etching rate of MoSi2 decreases as 02 increases, but in the vicinity of the resist 14, 02 is consumed to oxidize the resist itself. That is, the O2 depth near the resist remains low, and therefore the etching rate of MoSi2 becomes faster in this region. As a result, the MO8!2 film 13 is etched along the outer periphery of the resist pattern 14. The etching width is approximately 0.5 μm.

Next, using the pattern of the MoSi2 film 13 as a mask, the oxide film 12 and the silicon substrate 11 are etched to form a deep groove 16 as shown in FIG. 3(C). Then, as shown in FIG. 3(d), oxidation If! After removing J12, a thin oxide film 17 is formed on the surface, and a polysilicon film 18 which becomes an electrode is further formed to form a capacitor.

[Problems with back m technology]

In such conventional techniques, the etching rate varies greatly depending on the partial pressure of Mi in the gas system, so that the etching controllability is not good. In other words, if the oxygen partial pressure is too low, all of the MoSi2 except a part of the resist 1 will be etched. On the other hand, if the oxygen partial pressure is too high, etching will not proceed at all, and the resist will be etched away.

Since it is very difficult to control the oxygen partial pressure in J: sea urchin, the method shown in FIG. 3 has poor reproducibility.

Generally, the technology for etching only the area around the resist is still at an immature stage, and it is difficult to apply it to actual processes.

(Object of the Invention) The present invention was made in order to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can realize a groove structure on a semiconductor substrate with good reproducibility. do.

〔Effect of the invention〕

In order to achieve the above object, the present invention provides a first film (for example, silicon nitride film + silicon oxide film) on the surface of a semiconductor substrate.
a second step of patterning this first film to form a desired pattern; depositing a filling material (for example, polycrystalline silicon) on the sidewalls of the pattern;
a third step of leaving the structure, a fourth step of forming a second film (for example, a silicon oxide film) on the surface of the structure obtained in the third step, and etching the second film from the surface. Provided is a method for manufacturing a semiconductor device, comprising a fifth step of exposing the top of the embedding material, and a sixth step of etching the embedding material and the semiconductor substrate using the first and second films as masks. .

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2 of the accompanying drawings. FIGS. 1(a) to 1(Fl) are cross-sectional views showing one embodiment of the manufacturing process.

First, a lower insulating film 22 such as nitride wA is placed on a silicon substrate 21.
is formed, and an upper insulating film 23 such as an oxide film is formed thereon. Then, only the upper insulating film 23 is patterned to obtain a shape as shown in FIG. 1(a). Furthermore, this insulation g! The thickness of 122 and 23 is, for example, 1
,000 people and 4,000 people and B < is desirable.

Further, when patterning the insulating film 23, it is preferable that the pattern shape is a hole of 1 μm×lμ7rL.

Next, as shown in FIG. 1(b), about 40,001 layers of polycrystalline silicon 24 as a filling material is deposited. and R
The polycrystalline silicon 25 is etched by IE (this process is called edgeback) and remains only on the inner wall of the upper insulating film 23 as shown in FIG. 1(C). At this time, the width of the remaining polycrystalline silicon 25 is about 3000.

Next, an insulating film 26 such as an oxide film is formed using io, ooo.
i do Since the accumulated insulation II0 (oxide film) 26 is thick, the surface of the oxide film 26 has a gentle shape as shown in FIG. 1(d).

Next, when the oxide film 26 is etched back by RIE,
As shown in FIG. 1(e), the oxide film 27 remains in the center of the hole, and the surface of the polycrystalline silicon 25 is exposed. Then, using the oxide film 27 and the upper insulating film 23 as a mask, the polycrystalline silicon 25 whose top is exposed and the lower insulating film F12 immediately below it are removed.
2, and the structure shown in FIG. 1(f) is made into 1! '7
Ru.

Subsequently, the silicon substrate 21 is etched to a depth of 3 μm by RIE to obtain a structure in which grooves 28 are formed as shown in FIG. 3 (C+). Insulating film 2 such as oxide film or nitride film
2.23.27 was removed using a suitable etching agent,
A gate 1-M film 29 and a gate electrode 30 are formed to obtain a structure as shown in FIG.

This provides a capacitor for dynamic memory. FIG. 2 is a three-dimensional perspective view of the structure shown in FIG. 1(g).

The present invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment, the nitride IFJ 22 is formed on the semiconductor substrate 21 and the oxide film 23 is provided thereon. It's okay. Further, in the above embodiment, polysilicon was used as the filling material left on the side wall of the pattern, but a high melting point metal such as molybdenum or tungsten may also be used. Further, the insulating film is not limited to a silicon oxide film or a silicon nitride film, but may be any film as long as it can be selectively etched.

Further, in the above embodiment, an oxide film is used as the insulating film 26, but for example, an oxide film doped with phosphorus may be stacked to form a 9
By performing heat treatment at 00° C. or higher and melting this film, it is possible to obtain an even flatter film. Use of such a film facilitates pattern formation in subsequent steps.

The present invention can be widely applied not only to the quadrupole structure of a dynamic memory but also to element isolation on a semiconductor substrate.

〔Effect of the invention〕

As described above, in the present invention, the embedding material (for example, polysilicon) remains on the sidewall of the pattern using the already established etchback technique, and then the embedding material and the substrate underneath are etched. Thus, a method for manufacturing a semiconductor neck can be obtained that can realize a structure similar to the conventional one with good reproducibility.

Further, there is an advantage that the number of mask steps is only one, as in the conventional example. Furthermore, in the conventional technology, grooves are formed on the outside of the resist pattern, but in the case of the present invention, the grooves can be formed on the inside of the first resist pattern. This has the advantage that the size of the groove can be made finer.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of each manufacturing process showing an embodiment of the present invention;
FIG. 2 is a three-dimensional perspective view of the structure shown in FIG. 1(q), and FIG. 3 is a sectional view of each step showing a conventional manufacturing method. 21...Silicon substrate, 22...Lower insulating film (nitrogen film), 23...Upper insulating TI! A (FF film), 24
...Polycrystalline silicon, 25...Remaining polycrystalline silicon, 26...Insulating film (oxidized!J), 27...Remaining insulating film, 28...Trench. Applicant's agent Kiyoshi Inomata b I Kunimo 2 Figure

Claims (1)

[Claims] 1. A first step of forming a first film on the surface of a semiconductor substrate; a second step of patterning this first film to form a desired pattern; a third step of depositing and leaving the embedding material on the side wall; a fourth step of forming a second film on the surface of the structure obtained in this third step; a fifth step of etching away the top of the embedding material, and etching the top of the first and second embedding materials;
a sixth step of etching the embedding material and the semiconductor substrate using the film as a mask. 2. The first step includes forming a lower film on the surface of the semiconductor substrate, and forming an upper film on the lower film, and the second step includes forming the upper film on the surface of the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, comprising the step of patterning to form a desired pattern. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the lower film is a silicon nitride film, and the upper film is a silicon oxide film. 4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the embedding material is polycrystalline silicon. 5. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the second film is a silicon oxide film.