JPS6161411B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Among the instructions used in microcomputers (particularly 4-bit systems) is a skip instruction. This means that when the condition specified in this skip instruction is met, the instruction placed next to this skip instruction is skipped (ignoring the next instruction), and then the next instruction is executed. This is an instruction that performs processing that leads to the execution of an instruction (second instruction counting from the skip instruction). For example, now "A register is 0"
If we arrange in order a skip instruction that says "skip when ," and a branch instruction that follows this skip instruction that says "branch to address X," we get
When the A register is 0, the branch instruction is skipped and the branch is not executed, but when the A register is not 0, the next branch instruction is executed and the branch is executed to the X address. Accordingly, these two
By arranging the two instructions as above, A
If the register is not 0, branch to address
It is possible to configure a conditional branch instruction that does not branch (executes the next instruction) when . This skip instruction also executes the next instruction only when the condition specified by the skip instruction is not met by combining various other instructions. When this holds true, the command can be ignored. By using a general conditional jump instruction and selecting the next instruction after this conditional jump instruction as the jump destination, the same effect as this skip instruction can be obtained. Although there is the advantage of being able to specify the jump destination, it is necessary to specify the jump destination address. On the other hand, the skip instruction has the advantage that it can be used without specifying the address of the next instruction after the skip instruction at all, no matter how many bytes the next instruction to ignore is. Skip instructions for performing such processing are widely and conveniently used, especially in 4-bit microcomputers that have fewer types of instructions. Furthermore, in addition to the above-mentioned skip command, the process of ignoring a certain command can also be effectively used in the following cases.

In other words, if instructions of the same type are stored in memory in order, one instruction at the address specified first will be executed, and if the next instruction is defined as the same type of instruction as the first instruction. If the command has been executed, this function ignores this command (the second command) and proceeds to the next command (without executing this command). With such a function, you can use it conveniently as follows. For example, at the beginning of the current subroutine, put an instruction to put 3 in the A register, the second instruction put 4 in the A register, and then the third instruction put 5 in the A register.
Line up the commands to place . Suppose that a routine is then placed that performs processing using the contents of the A register as a parameter. When entering this subroutine now, if you enter from the first instruction to put 3 in the A register, this subroutine will first put 3 in the A register, but the next instruction, which is the instruction to put 4 in the A register, is as described above. Since it is the same type of instruction (this is defined as the same type of instruction) as the first executed instruction to place 3 in the A register, it is ignored by the above function and the next A
Proceed with the instruction to place 5 in the register. However, since this instruction is of the same type as the previous instruction, it is ignored, and in this case, the subroutine is executed with the initially given 3 as the value of the A register and that as a parameter. become. However, when entering this subroutine for the first time, if it is entered from an instruction to place 4 in the second A register, the subroutine will be executed with 4 as a parameter because of the same processing as described above. Become. Similarly, when this subroutine is entered from an instruction to place 5 in the third A register, this subroutine is executed with 5 as a parameter. In this way, when entering a subroutine, you can easily create a subroutine that performs processing with different parameters simply by changing and specifying the first entry address. In this way, if a group of instructions are defined as instructions of the same type, and instructions of the same type appear consecutively, the above-mentioned function executes the first instruction but ignores the subsequent instructions. We will call this the command stacking function.

When performing the above-mentioned skip command or instruction stacking function, if the appropriate conditions are met (i.e., in the case of a skip instruction, if the conditions specified by this command are met, and if the instruction stacking function is executed) In a conventional microprogram control device, when the condition that an instruction is the same type of instruction as the previous instruction is established, the instruction is ignored during the execution of the instruction that should be ignored. The method is to activate a prohibition circuit that prohibits the execution effect, thereby rendering the command ineffective. For this reason, for example, if you want to make an instruction that requires 6 machine cycles to execute have no effect, in conventional devices, even if you make it have no effect, it will take the same 6 machine cycles as if it were executed normally. This method has the disadvantage that machine cycles are expended before proceeding to the next instruction, and the processing time is longer than necessary. It is an object of the present invention to provide a microprogram control device that eliminates such drawbacks.

The present invention includes a determination circuit that determines whether an instruction read from a memory is an instruction that should be invalidated, and a determination circuit that determines whether an instruction read from a memory is an instruction that should be invalidated. and a circuit that updates the contents of a program counter in a smaller number of machine cycles than the number of machine cycles originally required for the instruction.

Next, the microprogram control device of the present invention will be explained in detail using the drawings. First, the case of a skip instruction will be explained, and then one embodiment of the present invention will be explained. FIG. 1 is a block diagram for explaining the case of a skip instruction. Reference numeral 1 indicates a microinstruction memory circuit. When a certain instruction is executed, the first byte of this instruction at the address specified by program counter 3 is first read from among the microinstructions stored in this instruction in the first machine cycle of that instruction. Stored in instruction register 2. When the first byte of the microinstruction is thus read into the instruction register 2, it is decoded by the decoder 4, and the control circuit 5 decodes it depending on whether this instruction is a 1-byte, 2-byte, or 3-byte instruction, etc. , controls the program counter control circuit 6 to increment the contents of the program counter 3 by one for each machine cycle required to further decode this instruction, and stores all bytes belonging to the instruction in the instruction register. 2 are sequentially read and decoded. In this way, the execution control circuit 5 executes the process specified by this decoded microinstruction. Thus, after a further number of machine cycles necessary for the execution of this instruction have elapsed, the control circuit 5, via the program counter control circuit 6, further increments the contents of the program counter 3 by one. Then, in the next machine cycle, the first byte of the next instruction at the address specified by the contents of the program counter 3 is read out, and execution proceeds to the next new instruction.
Now, suppose that a skip instruction is read into instruction register 2. This is decoded by the instruction decoder 4 as described above, but by specifying that this is a skip instruction, the logic level of the skip instruction designation line 7 is set to "1". Further, a portion of this skip instruction specifying a skip condition is supplied to a skip condition selection circuit 8, and the condition signal specified by this skip instruction is selected from among various skip condition signals 9. (This condition signal 9
For example, if the content of the A register mentioned above is 0, the logic level becomes "1", and if the content of the A register is not 0, the logic level becomes "0", or a specified signal. Various condition signals are included, such as a signal whose logic level becomes "1" when there is input data in the port that has been input, and a signal whose logic level becomes "0" when there is no input data. ) The condition signal selected by the skip condition selection circuit 8 is combined with the signal on the skip instruction designation line 7 using an AND circuit 10 and applied to the set terminal of the flip-flop 11.

Therefore, flip-flop 11 is set when the skip instruction is decoded and the condition specified by the skip instruction is met. Now, when the above skip command processing is completed, the control circuit 5 increments the contents of the program counter 3 by 1 via the program counter control circuit 6. Then, in the next machine cycle, the first byte of the instruction starting from the address next to this skip instruction is read into the instruction register 2. By decoding the first byte of a certain instruction in this way,
Information on how many bytes this instruction consists of can be obtained, so extract the information that specifies the number of bytes of this instruction and add it to the byte count output line 1.
2 to one input of the adder 13. The other input of this adder 13 is supplied with the contents of the program counter 3. Now, the execution control circuit 5 reads the first byte of the instruction in this way,
When the byte number of the instruction has been decoded and the adder 13 has completed adding the byte number input and the contents of the program counter 3, a program counter write pulse is output via the program counter write pulse line 14. do. This program counter write pulse line 14
and the output line of the flip-flop 11 are combined in a second AND circuit 15, and thus only when the flip-flop 11 is set (i.e., the previous instruction is a skip instruction and the skip condition is satisfied). only occasionally)
At the output of the second AND circuit 15, the write pulse outputted via the program counter write pulse output line 14 appears. This write pulse controls the program counter control circuit 6 to write the output of the adder 13 into the program counter 3. Thus, the contents of the program counter 3 specify the first byte of the second instruction counted from the skip instruction. The above processing is generally completed within the machine cycle when the first byte of the instruction following the skip instruction is read. Now, the first byte of the second instruction thus specified is read out to the instruction register 2 in the next machine cycle, and the first machine cycle of this instruction is entered again.

After generating a write pulse on the program counter write pulse line 14, the execution control circuit 5 generates a reset pulse near the end of this machine cycle, and sends it to the flip-flop via a reset pulse line 16. 11 to reset the flip-flop 11. Furthermore, the output of the flip-flop 11 becomes one input of the second AND circuit 15, and is also supplied as an instruction execution suppression signal to the execution control circuit 5 via the instruction execution suppression signal line 17. During the period when the logic level of the line is "1", except for the generation of the program counter write pulse and reset pulse, which are performed by the execution control circuit 5,
Other processing that should be performed as a result of decoding the first byte is suppressed. At the same time, the trailing edge of this signal is used to set the execution control circuit 5 to treat the byte read into the instruction register 2 as the first byte of a new instruction in the next machine cycle. Ru.

Of course, even if the skip instruction is decoded, if the condition specified by the skip instruction is not satisfied, the flip-flop 11 will not be set, so the instruction following the skip instruction will be executed according to the normal process mentioned above. Ru.

In this way, the function of the skip instruction described above is realized, but as is clear from the above explanation, if the skip condition of the skip instruction is satisfied, regardless of the instruction following the skip instruction ( Regardless of how many machine cycles it takes to properly execute this instruction, it always takes one machine cycle to disable that instruction and proceed to the second instruction.

The time relationship of the above-mentioned processing is shown in FIG. FIG. 2A shows an example of a conventional device. Assuming that the memory address where the skip instruction is stored is n, the contents of the program counter are such that the skip instruction is first read out at n. Assume that the skip condition is not satisfied. In the next machine cycle, the contents of the program counter become n+1 and the first byte of the next instruction is read. For example, suppose the next instruction is a 3-byte call instruction that takes 6 machine cycles to execute. In this case, the contents of the program counter advance to n+3 in the next machine cycle, read all three bytes of this instruction, and take another three machine cycles to complete execution of this instruction. Then, in the next machine cycle, the program counter advances to n+4, reads the first byte of the next instruction following the skip instruction, and starts executing this instruction anew. The processing in this case is shown in the second diagram of FIG. 2A when the skip condition is not satisfied. If the skip condition is not satisfied, a no-operation is repeated instead of the original call instruction during the machine cycle in which the instruction following the skip instruction (the call instruction) is to be executed, resulting in an effective no-operation. 6 without any processing
After spending a machine cycle, it begins executing the next next instruction. This is shown as a diagram when the skip condition is met in FIG. 2A.

On the other hand, the case of this embodiment is shown in FIG. 2B. In this case as well, when the skip condition is not satisfied, the process is exactly the same as in the conventional example, as shown in the figure. However, if the skip condition is met, as shown in the diagram when the skip condition is met in Figure 2B, the byte component of the instruction following the skip instruction ( advance by the number of bytes of the skipped instruction) at once,
(In this example, the program counter is incremented by 3 at once) to indicate that execution of the next instruction following the skip instruction will begin in the next machine cycle.

Note that in the above embodiment, by adding the contents of the program counter and the number of bytes of the next instruction after the skip instruction using an adder, the second
Although the address of the th instruction is directly obtained and thereby the skip processing is performed in the minimum processing time, it is also possible to perform the skip processing as follows instead.

That is, the output of the flip-flop 11 and the output of the byte number output line 12 are directly applied to the program counter control circuit 6, and when the output of the flip-flop 11 reaches logic level "1", the byte number output line It is also possible to adopt a configuration in which the contents of the program counter 3 are advanced in cycles faster than when normal instruction processing is performed by the number of bytes specified by the output of 12. By doing so, the skip processing when the skip conditions are satisfied can be made shorter than in the conventional device.

The above has described a configuration that makes a skipped instruction ineffective when using a skip instruction.However, a configuration for making a similar instruction ineffective is implemented when implementing the above-mentioned instruction stacking function. It can be used for.

FIG. 3 is a block diagram showing one embodiment of the present invention. Reference numeral 24 is a decoder having the same functions as the instruction decoder 4 in FIG. 1, but the following functions are added. In other words, when the first byte of a certain instruction is read into the instruction register 2, the decoder 24 determines whether the first byte of an instruction is newer than the information stored internally regarding the first byte of the instruction immediately before the instruction. Check whether the instruction is defined as the same type of instruction as the previous instruction. What is defined as the same type of instructions is defined so that the above-mentioned function of stacking instructions can be used as effectively as possible. Then, the decoder is configured to be able to detect the same type of instructions defined in this way as described above.

When the current instruction is detected as the same type of instruction as the previous instruction, a pulse of logic level "1" is output to the stacked instruction detection line 27. This detection line 27 is supplied to the set terminal of flip-flop 11, which has the same function as that in FIG. 1, to set it. Once this flip-flop 11 is set, the current contents of the program counter 3 are changed to the byte number output line 12, which outputs the number of bytes of this instruction, in much the same manner as described in FIG. The output of the adder 13 that adds the output is written to the program counter 3, and the execution of this instruction is sent to the instruction suppression signal line 1.
Suppress via 7. Thus, in the same way as explained using FIG. 1, the above processing is completed within the same machine cycle in which the first byte of this instruction is read, and in the next machine cycle, the first byte of the next instruction is Set byte to instruction register 2
can be read and immediately enter the machine cycle for that instruction.

Furthermore, as described in connection with FIG. 1, instead of using the adder 13 in FIG. 2, the output of the flip-flop 11 and the output of the byte number output line 12 are directly controlled by the program counter. In addition to the circuit 6, when the output of the flip-flop 11 becomes logic level "1", it is faster than normal instruction processing by the number of bytes specified by the output of the byte number output line 12. It is also possible to adopt a configuration in which the contents of the program counter 3 are advanced in cycles.

As described above, by using the present invention, when using the instruction stacking function to make the next instruction of the same type ineffective, it is possible to use a microprocessor that can process in a shorter processing time than conventional devices. This has the effect of providing a program control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the present invention.
2 is a diagram illustrating the progress of execution of a skip instruction, and FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 1... microinstruction memory circuit;
2...Micro instruction register, 3...Program counter, 4...Instruction decoder, 5...Execution control circuit, 6...Program counter control circuit, 7...
... Skip instruction designation line, 8 ... Skip condition selection circuit, 9 ... Skip condition, 10 ... AND circuit, 11 ... Flip-flop, 12 ... Byte number output line, 13 ... Adder, 14 ... Program counter Write pulse line, 15...
Second AND circuit, 16... Reset pulse line, 17... Instruction execution suppression signal line, 24...
Instruction decoder, 27...Vertical stack instruction detection line.

Claims (1)

[Claims] 1. A program counter that specifies the address of the memory where the microinstruction is stored, and determines whether the microinstruction read by this is an instruction with the same function as the previously read instruction. a decoder; when it is determined that the read instruction is an instruction having the same function as the previous instruction, means for disabling processing based on the microinstruction; and a first microinstruction of the disabled instruction. By adding the number information indicating the number of words of the instruction set in the word column and the contents of the program counter, the program counter is increased in a number of cycles less than the number of cycles required to execute the instruction. A microprogram control device comprising means for updating contents and accessing a next instruction.