JPS6159566B2 - - Google Patents
Info
- Publication number
- JPS6159566B2 JPS6159566B2 JP56089774A JP8977481A JPS6159566B2 JP S6159566 B2 JPS6159566 B2 JP S6159566B2 JP 56089774 A JP56089774 A JP 56089774A JP 8977481 A JP8977481 A JP 8977481A JP S6159566 B2 JPS6159566 B2 JP S6159566B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- transistor
- pull
- output terminal
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 claims 2
- 239000003990 capacitor Substances 0.000 description 22
- 230000007423 decrease Effects 0.000 description 4
- 238000007599 discharging Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
- Electric Double-Layer Capacitors Or The Like (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/181,318 US4376252A (en) | 1980-08-25 | 1980-08-25 | Bootstrapped driver circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5742231A JPS5742231A (en) | 1982-03-09 |
| JPS6159566B2 true JPS6159566B2 (en:Method) | 1986-12-17 |
Family
ID=22663780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56089774A Granted JPS5742231A (en) | 1980-08-25 | 1981-06-12 | Exciting circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4376252A (en:Method) |
| EP (1) | EP0046498B1 (en:Method) |
| JP (1) | JPS5742231A (en:Method) |
| CA (1) | CA1168317A (en:Method) |
| DE (1) | DE3166597D1 (en:Method) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133589A (en) * | 1981-02-12 | 1982-08-18 | Fujitsu Ltd | Semiconductor circuit |
| US5255240A (en) * | 1991-06-13 | 1993-10-19 | International Business Machines Corporation | One stage word line decoder/driver with speed-up Darlington drive and adjustable pull down |
| US5894241A (en) * | 1996-09-30 | 1999-04-13 | Cypress Semiconductor Corp. | Bootstrap augmentation circuit and method |
| US5828262A (en) * | 1996-09-30 | 1998-10-27 | Cypress Semiconductor Corp. | Ultra low power pumped n-channel output buffer with self-bootstrap |
| US6225819B1 (en) | 1998-03-17 | 2001-05-01 | Cypress Semiconductor Corp. | Transmission line impedance matching output buffer |
| US6384621B1 (en) | 2001-02-22 | 2002-05-07 | Cypress Semiconductor Corp. | Programmable transmission line impedance matching circuit |
| US6801063B1 (en) | 2003-06-17 | 2004-10-05 | Yazaki North America, Inc. | Charge compensated bootstrap driving circuit |
| US7888962B1 (en) | 2004-07-07 | 2011-02-15 | Cypress Semiconductor Corporation | Impedance matching circuit |
| US8036846B1 (en) | 2005-10-20 | 2011-10-11 | Cypress Semiconductor Corporation | Variable impedance sense architecture and method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3656004A (en) * | 1970-09-28 | 1972-04-11 | Ibm | Bipolar capacitor driver |
| US3751680A (en) * | 1972-03-02 | 1973-08-07 | Signetics Corp | Double-clamped schottky transistor logic gate circuit |
| US3987310A (en) * | 1975-06-19 | 1976-10-19 | Motorola, Inc. | Schottky diode - complementary transistor logic |
| US4002931A (en) * | 1975-06-27 | 1977-01-11 | Intel Corporation | Integrated circuit bipolar bootstrap driver |
| US4071783A (en) * | 1976-11-29 | 1978-01-31 | International Business Machines Corporation | Enhancement/depletion mode field effect transistor driver |
| US4191899A (en) * | 1977-06-29 | 1980-03-04 | International Business Machines Corporation | Voltage variable integrated circuit capacitor and bootstrap driver circuit |
| US4129790A (en) * | 1977-12-21 | 1978-12-12 | International Business Machines Corporation | High density integrated logic circuit |
-
1980
- 1980-08-25 US US06/181,318 patent/US4376252A/en not_active Expired - Lifetime
-
1981
- 1981-06-12 JP JP56089774A patent/JPS5742231A/ja active Granted
- 1981-07-07 CA CA000381265A patent/CA1168317A/en not_active Expired
- 1981-07-14 DE DE8181105491T patent/DE3166597D1/de not_active Expired
- 1981-07-14 EP EP81105491A patent/EP0046498B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0046498B1 (en) | 1984-10-10 |
| DE3166597D1 (en) | 1984-11-15 |
| US4376252A (en) | 1983-03-08 |
| CA1168317A (en) | 1984-05-29 |
| EP0046498A1 (en) | 1982-03-03 |
| JPS5742231A (en) | 1982-03-09 |
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