JPS6154264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for forming electrodes of semiconductor devices, particularly GaAsFETs.

GaAsFET is a semiconductor device that has a promising future as an ultra-high frequency device for microwave and other devices, and its manufacturing methods are being studied and improved in various ways.

The electrode formation method according to the present invention is also miniaturized.
It was devised to improve the quality of GaAsFETs, and a Schottky barrier type like this one is shown in Figure 1.
A cross-sectional view of the GaAsFET structure is shown.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n ^-
type GaAs epitaxial layer (thickness 2-3 μm), 3
is an n-type GaAs epitaxial layer (thickness 2000~3000
A source electrode 4, a drain electrode 5, and a gate electrode 6 are formed thereon, and the surface is covered with an insulating film 7.

By the way, in a GaAsFET having such a structure, the gate electrode 6 is usually formed by vapor-depositing aluminum, but when forming the aluminum into a fine shape with a width of about 0.7 μm, for example, there is a limit to the thickness. However, the aluminum electrode can only be formed to a thickness of 5,000 to 6,000 Å at most, and aluminum is mixed with moisture, oxygen, and
GaAs reacts and changes its quality, sometimes causing migration at the interface. Also, during use, oxidation progresses from the surface layer of the electrode where current easily flows, increasing the electrical resistance of the gate electrode itself. Problems are arising.

The present invention proposes a method for forming an extremely small metal gate electrode with a structure that does not alter the quality of such miniaturized gate electrodes.
The feature of the present invention is that metal layers are stacked in a multilayer structure in which the lowest layer of the gate electrode is an aluminum layer, and the upper layer excluding the aluminum layer is patterned to a first width by ion milling to partially remove the aluminum layer. a step of plating the upper surface of the metal layer of the gate electrode to be patterned with gold in a pattern having a second width wider than the first width, a step of selectively anodizing the exposed aluminum layer, and then plating with gold. Step of partially exposing the substrate surface by removing the anodic oxide layer in the source electrode formation region and drain electrode formation region using metal as a mask, and applying the source electrode and drain electrode to the exposed substrate surface using the gold plating layer as a mask. and a step of forming.

Hereinafter, the present invention will be explained in detail by one embodiment with reference to the drawings.

2 to 7 are sequential diagrams of the manufacturing process of the present invention. First, as shown in FIG. 2, aluminum layer 11, titanium layer 12, and platinum layer are formed on GaAs layer 10 by vapor deposition or sputtering. 13, gold layer 14
A photoresist film 15 having a width of 1 μm is selectively formed on the upper surface of the gate electrode region by selective patterning.

Next, as shown in FIG. 3, a photoresist film 15 is formed.
Using as a mask, the gold layer 14, platinum layer 13, and titanium layer 12 are etched away by ion milling. Ion milling is most suitable for etching adhered layers made of different materials as mentioned above.
The GaAs substrate is not etched, and the etched surface is smoother than chemical etching. In addition, since the lower layer is the aluminum layer 11, the aluminum layer has the effect of dissipating the charge accumulated on the surface due to ion milling, and since the etching rate of the aluminum layer is slow, the etching can be clearly stopped with the titanium layer. The aluminum layer is not overetched.

Next, as shown in FIG. 4, a photoresist film 1 is formed.
After removing the metal 14, a gold plating layer 16 with a thickness of about 1 μm is laminated on the metal 14. When a 1 μm thick plating layer is deposited in this way, a 1 μm thick plating layer is also deposited in the lateral direction, and the width extends by 1 μm on the left and right for a total of 3 μm.
m, and an overhanging gold plating layer 16 is formed on the gate electrode.

Next, as shown in FIG. 5, the exposed aluminum layer is anodized, and the aluminum layer on the bottom side of the platinum layer 13 and titanium layer 12, which have already been formed as part of the gate electrode, is also anodized. The width of the aluminum layer of the gate electrode is formed to a submicron width of about 0.6 μm. This anodization 17
An ammonium borate saturated solution was used, and the current density was about several mA/cm ³ , and the current value varied depending on the degree of side oxidation. In addition, the limit for the thickness of the aluminum layer to form a dense oxide layer is 1000 Å, and the anodic oxide layer formed in this way insulates the gate electrode, source electrode, and drain electrode, and protects the GaAs substrate. fulfills the role of

Next, as shown in FIG. 6, the anodic oxide layer is removed by reactive sputter etching using the gold plating layer 16 as a mask. Side etching is the least likely method because reactive sputter etching is etched by a synergistic physical and chemical action.

Next, as shown in FIG. 7, a gold-germanium alloy layer and then a gold layer are deposited from the upper surface to form a source electrode 18 and a drain electrode 19. There is no problem even if those layers are deposited on the gold plating layer 16 at that time.

The following steps are based on a known manufacturing method, and the above is the electrode forming method according to the present invention,
In this way, according to the present invention, the gate electrode width (gate length) is formed into a fine submicron pattern, the aluminum layer is made very thin, and the upper layer of the electrode is plated with highly conductive gold to increase the volume. It is made larger to reduce electrical resistance. This prevents the gate electrode from being heated and deteriorating in quality. On top of that, the anodic oxide layer of aluminum is a protective film with fewer interface states than the silicon oxide protective film deposited by CVD, so it does not deteriorate the FET characteristics.

Therefore, the present invention can be said to be excellent in that it allows the gate electrode of a GaAaFET to be formed extremely finely and to increase reliability.

[Brief explanation of the drawing]

FIG. 1 is a structural cross-sectional view of a GaAsFET, and FIGS. 2 to 7 are cross-sectional views of the process of the present invention. In the figure, 10 is a GaAs layer, 11 is an aluminum layer, 12 is a titanium layer, 13 is a platinum layer, 14 is a gold layer, 15 is a photoresist film, 16 is a gold plating layer,
Reference numeral 17 indicates an anodized layer, and 18 and 19 indicate a source electrode and a drain electrode, respectively.

Claims (1)

[Scope of Claims] 1. After depositing an aluminum layer on a semiconductor substrate and then depositing other metal layers in sequence, the other stacked metal layers except for the gate electrode forming portion are removed by ion milling. partially exposing the aluminum layer by patterning the aluminum layer to have a second width wider than the first width;
A step of selectively anodizing the exposed aluminum layer; Next, using the gold plating layer as a mask, the anodic oxide layer in the source electrode formation region and the drain electrode formation region is removed, and the substrate is removed. A method for manufacturing a field effect semiconductor device, comprising: partially exposing a surface of the substrate; and depositing a source electrode and a drain electrode on the exposed surface of the substrate using the gold plating layer as a mask.