JPH01184958A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to avoid such a trouble as an interelectrode short-circuit due to a falled-out thin-film protrusion by a method wherein the upper surface of a lower conductor layer pattern is exposed on the lower conductor layer pattern and at the same time, a bottle-shaped groove of a depth, which does not reach the surface of a substrate, is formed and an upper conductor layer along the lower conductor layer is adhered on the lower conductor layer using a resist layer as a mask. CONSTITUTION:A control developing is performed by a dipping method using a developing solution having a composition ratio of methyl isobutyl ketone(MIBK) : isopropyl alcohol(IPA)=1:3. Thereby, the upper surface of a WSi layer pattern 4 is exposed, and a groove 8 like a bottle which does not reach the surface of a substrate and has an aperture width Lg3 of about 1-0.8mum and a wider bottom. Then, after the upper surface of the pattern 4 is cleaned by ion milling or plasma etching treatment, a titanium(Ti) layer 9, which is used as a diffusion barrier against gold(Au), and an Au layer 10, which is used as the main conductor layer of the top layer, are continuously deposited on a resist layer 6 including the upper surface of the pattern 4 exposed in the above groove 8. Thereby, the edge parts of the upper surface of the layer 10 deposited on the upper part of the pattern 4 are formed into the form of a slant face and a protruding part is never formed.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, particularly a method for forming a laminated structure electrode disposed in a semiconductor device, by simplifying the process and preventing a decrease in manufacturing yield and reliability. In order to provide a method for forming a laminated electrode, a lower conductor layer pattern having an electrode shape is formed on a substrate, and on the substrate having the lower conductor layer pattern, the lower layer is a high-sensitivity resist layer and the upper layer is a low-sensitivity resist layer. Consisting of resist layer 2
forming a resist layer having a layered structure, exposing the resist layer to a pattern having a size equal to or smaller than the lower conductor layer pattern overlapping the lower conductor layer pattern under controlled exposure conditions; Developing the layer by controlling the development time,
The resist layer above and in the vicinity of the upper conductor layer pattern is selectively removed to a depth where the upper surface of the lower conductor layer pattern is exposed and the substrate surface is not exposed, and the exposed lower conductor layer is removed. depositing an upper conductor layer on the upper surface of the layer pattern and the resist layer, dissolving and removing the resist layer, and selectively lifting off the upper conductor layer on the resist layer;
The method includes the step of selectively residually depositing the upper conductor layer on the lower conductor layer pattern.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a laminated structure electrode disposed within a semiconductor device.

As a Schottky gate electrode material for a gallium arsenide (GaAs) FET, a low-resistance metal material, particularly aluminum (AI), has been widely used in the past in order to improve the high frequency characteristics of the FET.

However, the above AI gate has the problem of deterioration over time due to electromigration, reaction with oxygen, reaction with the substrate material, that is, GaAs, and the like.

Recently, in order to improve the reliability life of GaAsFETs, electrode materials containing high melting point metals that are stable at the same temperature, do not react with oxygen or substrate materials, and do not easily cause electromigration, such as tungsten silicide (
W Si ) is beginning to be used.

Since this W S i has a resistivity that is about two orders of magnitude higher than that of conventionally used AI, when used for a gate electrode, for example, as schematically shown in FIG. The gate electrode 22 has a structure in which the i-electrode 53 is laminated with a conductive layer 54 having a low resistivity, such as a gold (Au) layer 54.
This reduces the series resistance of the circuit, thereby improving high frequency characteristics. Note that 51 in the figure indicates a GaAs substrate.

[Conventional technology]

Conventionally, the above WSi,! As shown in FIG.
After forming the Si electrode 53, a silicon dioxide (SiO□) film 54 for a mask having a thickness a of approximately 5000 mm, which is approximately equal to the lower layer electrode 53, is formed on the substrate by a low pressure vapor deposition (low pressure CvD) method. Then, as shown in FIG. 4 (bl), a resist layer 55 is deposited on the substrate to a thickness such that the upper surface is flat, and then, as shown in FIG. SiO□ for masks
The entire surface of the resist layer 55 is etched (etched back) using an anisotropic dry etching method until the top of the film 54 is exposed, and then the remaining resist layer 55 is etched back using an active ion etching (RIE) process as a mask. After removing the entire SiO□ film 54 in the exposed area, the resist layer 55 is removed, and as shown in FIG. 4(d), the W S
An opening 56 is formed in the 5in2 film 54 on the i-lower electrode 53 and extends along the electrode.

Next, as shown in FIG. 4 (el), a titanium (Ti) layer 57 with a thickness of approximately 1000 mm and a low resistance layer 57 and a low resistance layer are formed over the entire surface of the substrate including the inner surface of the opening 56.
A 0-thick U layer 58 is continuously deposited on the Au layer 58, and then a W Si electrode 5 is deposited on the Au layer 58 as shown in FIG. 4(f).
A resist pattern 59 is formed on top of the WSi electrode 53, and the resist pattern 59 has a shape that is almost not sharp with the WSi electrode 53. Then, using the resist pattern 59 as a mask, ion milling is performed to expose the Au layer 58 and the Ti body layer 7. After removing the resist pattern 59, a low-resistance Au layer 58 is formed on the W Si electrode 53 via the Ti body layer 7 which serves as a diffusion barrier for the sieve, as shown in FIG. A gate electrode 52 having a stacked layered structure was formed.

[Problem that the invention seeks to solve]

However, according to the above conventional method, pinholes are likely to occur in the resist layer 55 when the resist layer 55 is etched back.1. For this purpose, the mask S on the WSi electrode 53 is
In the RIE process when forming the openings 56 in the i0g film 54, holes that cause element deterioration are often formed in the mask SiO□ film 54.
In the ion milling process when patterning the i-body layer 7, these milled metals adhere to the side surfaces of the resist pattern 59 used as a mask, as shown in FIG. However, these metal thin film-like protrusions 60 are formed on the edges of the pattern of the Au layer 58, and in a later process, the thin film-like protrusions 60 fall off, causing short circuits between electrodes, etc., and damaging the device. There was a problem of lowering manufacturing yield and reliability.

Furthermore, as explained above, the conventional method has the problem that the steps are complicated and the manufacturing steps are long.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for forming a laminated electrode that simplifies the process and prevents a decrease in manufacturing yield and reliability.

[Means to solve the problem]

The above problem is that when forming an electrode with a laminated structure in which an upper conductor layer is laminated on a lower conductor layer, an upper conductor layer pattern having an electrode shape is formed on the substrate, and the lower conductor layer is A resist layer having a two-layer structure consisting of a high-sensitivity resist layer as a lower layer and a low-sensitivity resist layer as an upper layer is formed on a substrate having a layer pattern, and the resist layer is overlaid on the lower conductor layer pattern, and the lower layer is overlaid on the lower conductor layer pattern. A pattern having a size equal to or smaller than the upper conductor layer pattern is exposed by controlling the exposure conditions, and the resist layer is developed by controlling the development time to remove the resist above and in the vicinity of the upper conductor layer pattern. The layer is selectively removed to a depth where two sides of the lower conductor layer pattern are exposed and the substrate surface is not exposed, and the upper layer is removed on the upper surface of the exposed lower conductor layer pattern and on the resist layer. Depositing a conductor layer, dissolving and removing the resist layer, and selectively lifting off the upper conductor layer on the resist layer to selectively deposit the upper conductor layer on the upper conductor layer pattern. A semiconductor device according to the present invention having a residual deposition step!
! ! How to make it will be decided.

[For production]

That is, in the present invention, when a part of a resist layer with a 2N structure consisting of a high-sensitivity resist layer as a lower layer and a low-sensitivity resist as an upper layer that does not mix with the high-sensitivity resist layer is exposed and developed,
A technique for forming a resist mask that is easy to lift off by forming an octopus-shaped opening in which a lower region made of a high-sensitivity resist expands from an opening made of a low-sensitivity resist, and the exposure amount and development time of the resist layer. Taking advantage of the fact that it is possible to leave a resist layer of the required thickness at the bottom of the octopus-shaped opening by controlling the Then, an octopus-shaped groove is formed that exposes the upper surface of the upper conductive layer pattern and has a depth that does not reach the substrate surface, and the upper conductive layer is formed on the lower conductive layer by a lift-off method using the resist layer as a mask. A layered electrode is formed by depositing an upper conductor layer along the body layer.

According to this method, a mask insulating film is not used, so deterioration of device performance due to pinholes when forming a contact window on the mask insulating film is avoided, and the upper electrode layer is patterned by a lift-off method. Therefore, the thin film-like protrusions of the electrode layer are not formed at the edges of the upper electrode layer pattern, and problems such as short circuit between electrodes due to the thin film-like protrusions that have fallen off are avoided.

Furthermore, since the number of steps is significantly reduced, the manufacturing process is simplified.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

1(a) to 1(g) are process cross-sectional views of one embodiment of the present invention, and the second figure is a GaAsF[!] formed according to the present invention. It is a schematic plan view of T.

Identical objects are indicated by the same reference numerals throughout the figures.

When forming a GaAsFET having a gate electrode with a stacked structure in which the lower four conductor layers are WSi layers and the upper conductor layer strength is <Au layer using the method of the present invention, see FIG. 1 (al). n-type GaAs active layer 2 on semi-insulating GaAs substrate 1
Using a substrate 3 to be processed on which is formed, for example, a width (L
g+) = 1 μm, thickness (t) = approximately 0.5 μm,
Tungsten silicide (W) with gate electrode shape
S i ) forming layer pattern 4;

FIG. 1 (See BL) Next, a polymethyl methacrylate (PM, MK)-based positive resist for EB, such as CMR, is applied as a lower high-sensitivity resist layer 5 over the entire surface of the substrate 3 to be processed having the WSi layer 4. (manufactured in-house) is spin-coded to a thickness of about 1 μm on the flat part, and then baked at 150 to 200° C. for about 30 minutes.

Refer to FIG. 1(C) Next, as an upper low-sensitivity resist layer 6 on the substrate,
A PMMK-based EB positive resist 0EBR (manufactured by Tokyo Ohka) is spin-coded to a thickness of about 0.3 μm, and then baked at 150 to 200° C. for about 20 minutes.

Figure 1! d) Reference Then, using an EB exposure device, W S is applied to the resist layer.
A pattern having a width gz of, for example, about 0.8 μm, which is less than the width Lg1 of the WSi layer body layer 4, is formed so as to overlap the i-layer pattern 4 at an exposure dose of, for example, 7.5XIO-.
Exposure is carried out by controlling the exposure to approximately 'Ω/cm''.As shown by the chain line in the figure, 1. it is narrow in the upper low-sensitivity resist layer 6, widens in the lower high-sensitivity resist layer 5, and the bottom part is A photosensitive area 7 is formed that does not reach the substrate surface.

See FIG. 1(e) then for example methyl isobutyl ketone (MIBK):
Isobu! ] Perform control development for about 2 minutes using a developer solution containing building alcohol by the immersion method. As a result, as shown in the figure, W Si
A groove 8 is formed in which the upper surface of the layer pattern 4 is exposed, the bottom part does not reach the substrate surface, the opening width Lgz is about 1 to 0.8 μm, and the lower part widens into an octopus pot shape.

Refer to FIG. 1 ( ). Next, a metal layer is deposited as an upper electrode material and a W S
After cleaning the upper surface of the WSi layer pattern 4 by ion milling or plasma etching to improve the adhesion with the i layer pattern 4, the groove 8 is
A thickness of 1000 mm is applied to the resist layer 6, including the upper surface of the WSi layer body layer 4 exposed inside, to serve as a diffusion barrier for gold (Au).
A titanium (Ti) layer 9 having a thickness of approximately 5000 nm and an Au layer 10 having a thickness of approximately 5000 nm, which will serve as the upper main conductive layer, are successively deposited.

At this time, the resist layer formed on the W S 4-layer pattern 4? 14 Since 8 has the octopus pot top as described above, the vapor deposited metal layer (9 and 10) on the resist layer 6 and the vapor deposited metal layer (9 and 10) on the WSi layer body layer 4 are continuous. Since the inside of the groove 8 is wider than the opening, the upper edge of the Au layer 10 deposited on the WSIS 1-layer pattern 4 is sloped and has a protrusion as shown in the figure. Never. Furthermore, since the bottom of the groove 8 does not reach the substrate surface, that is, the surface of the n-type GaAs active layer 2, the lower part of the metal layer (9 or IO) deposited on the W S four-layer pattern 4 is the n-type GaAs active layer. It is formed at a position spaced apart from the top surface of 2.

Referring to FIG. 1(g), the substrate is then immersed in a predetermined resist stripping solution to dissolve and remove the resist layers 5 and 6. At the same time, the Ti body layer and the 40 layer 1o on the resist layer are lifted off to form a Schottky bond in the lower layer. The thickness of the main conductive layer (auxiliary U layer 1
A Schottky gate electrode 11 having a stacked structure in which 0 is deposited is formed.

After referring to FIG. 1 (hl), a source electrode 12 and a drain electrode 13 having a two-layer structure of, for example, AuGe/Au are formed by a conventional method to complete a GaAsFET according to the present invention.

FIG. 2 is a schematic plan view showing the completed state of the GaAs FIET. As shown in the figure, the upper conductor layer, i.e., the Ti body layer and the Au layer IO are usually formed on the striped part functioning as the gate of the W Si layer pattern 4, and the gate F T electrode is 11 series resistance is reduced.

As shown in the examples above, according to the method of the present invention, an electrode with a laminated structure can be produced by: 1) forming a lower conductor layer pattern; ii)
) photo process, iii) vapor deposition, iv) refresh-me-off, and is formed by the conventional method i) formation of lower conductor layer pattern, ii) formation of CVD insulation single layer film for mask, iii) photo process, iv) This process is greatly simplified compared to the seven steps of etching, v) vapor deposition, vi) photo process, and vii) ion milling.

〔Effect of the invention〕

As explained above, according to the present invention, an insulating film mask is not used when forming the upper conductive layer pattern, so that the contact window of the insulating film mask is caused by pinholes, which conventionally tend to occur during etching. Deterioration of the device performance is avoided, and since the upper surface edge of the laminated electrode is formed in a gentle slope shape and the thin film-like protrusion of the upper conductor layer is not formed on the edge, the thin film-like protrusion is prevented from forming on the edge. Since short-circuit failures such as short-circuits between electrodes due to falling off are avoided, the manufacturing yield and reliability of semiconductor devices having stacked electrodes such as GaAsFETs are improved. Furthermore, since the manufacturing process is simplified, the manufacturing steps are shortened.

[Brief explanation of the drawing]

1 (al to h) are process sectional views of an embodiment of the present invention, FIG. 2 is a schematic plan view of a GaAsFET according to the method of the present invention, FIG. 3 is a schematic perspective view of an interlayer structure electrode, Figure 4 (al~(+'cl) is a cross-sectional view of the process of the conventional method, and Figure 5 is a schematic perspective view showing the problems of the conventional method. layer,
3 is the substrate to be processed, 4 is the WSi layer, and 5 is the high-sensitivity resist! , 6 is a low-sensitivity resist layer, 7 is a photosensitive region, 8 is a groove, 9 is a Ti layer, 10 is an AU layer, 11 is a laminated Schottky gate electrode, 12 is a source electrode, and 13 is a drain electrode.

Claims (1)

[Claims] When forming an electrode with a laminated structure in which an upper conductor layer is laminated on a lower conductor layer, a lower conductor layer pattern having an electrode shape is formed on a substrate, and the lower conductor layer is stacked on the lower conductor layer. A resist layer having a two-layer structure consisting of a high-sensitivity resist layer as a lower layer and a low-sensitivity resist layer as an upper layer is formed on a substrate having a layer pattern, and the resist layer is overlaid on the lower conductor layer pattern, and the lower layer is overlaid on the lower conductor layer pattern. A pattern having a size equal to or smaller than the conductor layer pattern is exposed by controlling exposure conditions, and the resist layer is developed by controlling the development time to form a resist layer above and in the vicinity of the lower conductor layer pattern. is selectively removed to a depth where the upper surface of the lower conductor layer pattern is exposed and the substrate surface is not exposed, and the upper conductor layer is removed on the exposed upper surface of the lower conductor layer pattern and on the resist layer. and selectively lift off the upper conductor layer on the resist layer at the same time as dissolving and removing the resist layer to selectively residually deposit the upper conductor layer on the lower conductor layer pattern. 1. A method of manufacturing a semiconductor device, the method comprising a step of making a semiconductor device.