JPS6153853B2 - - Google Patents

Info

Publication number
JPS6153853B2
JPS6153853B2 JP53164876A JP16487678A JPS6153853B2 JP S6153853 B2 JPS6153853 B2 JP S6153853B2 JP 53164876 A JP53164876 A JP 53164876A JP 16487678 A JP16487678 A JP 16487678A JP S6153853 B2 JPS6153853 B2 JP S6153853B2
Authority
JP
Japan
Prior art keywords
lead wire
electrode
recess
semiconductor device
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53164876A
Other languages
Japanese (ja)
Other versions
JPS5591133A (en
Inventor
Toshio Kasuga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP16487678A priority Critical patent/JPS5591133A/en
Publication of JPS5591133A publication Critical patent/JPS5591133A/en
Publication of JPS6153853B2 publication Critical patent/JPS6153853B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79Apparatus for Tape Automated Bonding [TAB]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置にかかり、特に改良された
リード線を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved lead wire.

従来この種の半導体装置においては素子の複数
個の電極と接続するリード線の電極との接続面は
ほぼ平らであり、該電極とリード線が熱融着等の
方法で接続されていた。
Conventionally, in this type of semiconductor device, the connecting surface of a lead wire connecting a plurality of electrodes of an element to the electrode is substantially flat, and the electrode and the lead wire are connected by a method such as thermal fusion.

第1図は従来技術による半導体装置の断面図で
ある。
FIG. 1 is a sectional view of a semiconductor device according to the prior art.

通常のリードフレームもしくは樹脂フイルム4
に設けられかつ該フイルムの開孔6から張り出し
ているリード線3の先端が半導体素子1上の電極
2と熱融着又は熱圧着等の方法で接続されてい
る。リード線3は一般に銅、鉄、ニツケル、コバ
ール等或いはこれらの組み合わせによる合金材を
エツチングにより形成し、錫或いは金で表面にメ
ツキした層3′設ける。このようなリード線3を
半導体素子1の電極2と接続した場合、リード線
3の表面にメツキされた層3′(例えば錫)が電
極2(例えば金)との間で合金物(例えば金−錫
共晶合金)等を形成して電気的機械的な接合が行
なわれる。しかしながら上記合金物を形成する際
に接続時の熱によつて溶融或いは軟化した金属が
流れだし素子1とリード線3との間に金属粒塊5
を生じさせる。該粒塊5は異常な電気的接続をも
たらして半導体装置を破損させるという欠点を有
していた。
Ordinary lead frame or resin film 4
The tip of a lead wire 3 provided in the film and protruding from the opening 6 of the film is connected to the electrode 2 on the semiconductor element 1 by a method such as thermal fusion bonding or thermocompression bonding. The lead wire 3 is generally formed by etching an alloy material such as copper, iron, nickel, Kovar, etc. or a combination thereof, and has a layer 3' plated with tin or gold on the surface. When such a lead wire 3 is connected to the electrode 2 of the semiconductor element 1, a layer 3' (for example, tin) plated on the surface of the lead wire 3 is formed between the electrode 2 (for example, gold) and an alloy (for example, gold). - a tin eutectic alloy), etc., and electrical and mechanical bonding is performed. However, when the alloy is formed, metal that has been melted or softened by the heat during connection flows out and metal particles 5 are formed between the element 1 and the lead wire 3.
cause The agglomerates 5 had the disadvantage of causing abnormal electrical connections and damaging the semiconductor device.

この種の金属粒塊の発生を防ぐ方法として種々
考えられた。第1に金属粒塊5を構成する合金の
量を少くする為にリード線3のメツキ層3′の厚
さを薄くすることである。通常用いられている錫
メツキの厚さは0.7μ前後である。これを0.5μ以
下にすることによつてかなりの改善がされる。し
かしながらリード線3の耐環境性が悪くなる。例
えば次工程以降の熱処理あるいは雰囲気によりリ
ード線3の半田濡れ性が悪くなるという欠点があ
つた。さらには合金量が少なくなる為リード線3
と電極2との接続が不充分となりオーブン不良が
発生しやすくなるという欠点を有していた。
Various methods have been considered to prevent the generation of this type of metal agglomerates. First, the thickness of the plating layer 3' of the lead wire 3 is reduced in order to reduce the amount of alloy constituting the metal granules 5. The thickness of the tin plating normally used is around 0.7μ. A considerable improvement can be made by reducing this to 0.5μ or less. However, the environmental resistance of the lead wire 3 deteriorates. For example, there was a drawback that the solder wettability of the lead wire 3 deteriorated due to the heat treatment or atmosphere after the next process. Furthermore, since the amount of alloy decreases, lead wire 3
This has the drawback that the connection between the electrode 2 and the electrode 2 is insufficient, and oven failure is likely to occur.

第2の方法は合金化する範囲を広げて単位面積
当たりの合金の量を少くすることである。通常の
接続加熱温度よりも高い温度で接続するとリード
線3のメツキ層3′は接続部近傍のみならずより
広い面積において合金層を作る為に金属粒塊5の
発生は抑えられる。又、発生したとしてもリード
線3と素子1との間を短絡させるほどには成長し
ないですむ。しかしながら、接続加熱温度を高く
すると素子1の特性及び素子電極2の素子に対す
る密着性に悪影響を及ぼすという欠点を有してい
た。
The second method is to widen the area to be alloyed and reduce the amount of alloy per unit area. When the connection is made at a temperature higher than the normal connection heating temperature, the plating layer 3' of the lead wire 3 forms an alloy layer not only in the vicinity of the connection part but also in a wider area, so that the generation of metal particles 5 can be suppressed. Further, even if it occurs, it does not need to grow to the extent that it causes a short circuit between the lead wire 3 and the element 1. However, there was a drawback that increasing the connection heating temperature adversely affected the characteristics of the element 1 and the adhesion of the element electrode 2 to the element.

本発明の目的は、上記欠点を除去、高信頼性で
安価な半導体装置を提供することである。
An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable and inexpensive semiconductor device.

本発明は複数個の電極を有する半導体素子と、
該半導体素子の電極にリードの先端部を圧着接続
してなる半導体装置において、前記リードの先端
部には前記電極に対向する位置から外れた近傍に
該リードを貫通しない凹部を設け、該凹部の表面
をメツキ層で覆い、このメツキ層で覆われた前記
凹部にて接続時の熱によつて溶融もしくは軟化し
た金属を表面張力によつて吸引することを特徴と
するものである。
The present invention provides a semiconductor element having a plurality of electrodes,
In a semiconductor device in which a tip of a lead is crimped and connected to an electrode of the semiconductor element, the tip of the lead is provided with a recess that does not penetrate through the lead in the vicinity away from the position facing the electrode; The surface is covered with a plating layer, and the metal melted or softened by the heat during connection is attracted by surface tension in the recessed portion covered with the plating layer.

本発明を実施例により説明する。第2図は本発
明の1実施例の半導体装置のリード線と電極の接
合部近傍の断面図である。テープ状の樹脂フイル
ムに設けられた開孔に張り出されたリード線13
は、接続すべき半導体素子11の電極12の1側
辺部近傍において凹部17が形成されている。凹
部17はフオトレジストをマスクとする通常の選
択エツチング法によつて容易に形成される。上記
リード線13はさらに錫メツキが施こされるが次
工程以降の熱処理(例えば樹脂封入時の150℃16
時間放置)による半田濡れ性への悪影響を防ぐ為
に1.0μ程度の厚い錫メツキ層13′を設ける。
The present invention will be explained by examples. FIG. 2 is a sectional view of the vicinity of the junction between the lead wire and the electrode of a semiconductor device according to an embodiment of the present invention. Lead wire 13 extending through an opening provided in a tape-shaped resin film
A recess 17 is formed near one side of the electrode 12 of the semiconductor element 11 to be connected. The recess 17 is easily formed by a conventional selective etching method using a photoresist as a mask. The lead wire 13 is further tin-plated, but heat-treated in the next process (for example, at 150°C 16°C during resin encapsulation).
A thick tin plating layer 13' of about 1.0 .mu.m is provided in order to prevent adverse effects on solder wettability due to long standing times.

上記錫メツキされたリード線13は例えば金で
作られた半導体素子電極12との間で金−錫の共
晶合金を形成して接続される。この時に接続時の
熱によつて溶融或いは軟化した金属15が流れだ
すが表面張力によりリード線13の凹部17に吸
引され素子11とリード線13との間を短絡させ
る金属粒塊は生じなくなる。この為に接続時の溶
融或いは軟化した金属をリード線13の接続部の
みならずより広い面積において合金層として広げ
る為に接続時の加熱温度を高くする事をせずにす
ますことができ、高温加熱による素子特性及び電
極の素子への密着性に悪影響を防げる。
The tin-plated lead wire 13 is connected to the semiconductor element electrode 12 made of gold, for example, by forming a gold-tin eutectic alloy. At this time, the metal 15 melted or softened by the heat during connection flows out, but is attracted to the recess 17 of the lead wire 13 due to surface tension, and metal particles that cause a short circuit between the element 11 and the lead wire 13 are no longer generated. For this reason, it is not necessary to increase the heating temperature during connection in order to spread the melted or softened metal as an alloy layer not only at the connection part of the lead wire 13 but also over a wider area. This prevents adverse effects on element characteristics and adhesion of electrodes to elements due to high-temperature heating.

凹部17の形状は上記実施例以外に種々の形状
をとつても本発明の効果は全く変わないことは明
きらかであり、さらに凹部の配置も上記実施例に
限られるものではない。
It is clear that the effects of the present invention will not change at all even if the shape of the recess 17 is varied in addition to the above embodiments, and furthermore, the arrangement of the recesses is not limited to the above embodiments.

第3図は本発明にかかるリード線の接続部近傍
の凹部の他の配置例を示したリード線と半導体素
子の電極との接続部近傍の断面図である。
FIG. 3 is a cross-sectional view of the vicinity of the connection between the lead wire and the electrode of the semiconductor element, showing another arrangement example of the recess near the connection of the lead wire according to the present invention.

半導体素子21の電極22側辺部近傍に凹部が
形成されている。凹部27がリード線23と素子
電極22との接続時の熱により溶融或いは軟化し
て流れだす金属25を表面張力により吸引すると
いう効果は全く変らない。
A recess is formed near the side of the electrode 22 of the semiconductor element 21 . The effect that the recess 27 attracts the metal 25 that melts or softens and flows out due to the heat generated when the lead wire 23 and the element electrode 22 are connected by surface tension remains unchanged.

以上説明した実施例では素子電極が金、リード
線のメツキ層が錫の金−錫共晶合金接続方式を述
べたが素子電極が金に限らず錫、半田、亜鉛、ア
ルミニウム等、リード線が錫に限らず金、半田、
亜鉛、アルミニウム等の種々の金属でよく接続時
の熱により溶融或いは軟化する金属の組み合わせ
に効果があることは言うまでもないことである。
In the embodiments described above, a gold-tin eutectic alloy connection method is described in which the element electrode is gold and the plating layer of the lead wire is tin. Not only tin but also gold, solder,
It goes without saying that combinations of various metals such as zinc and aluminum, which melt or soften due to heat during connection, are effective.

以上説明したように本発明によれば、半田濡れ
性が充分な厚さのメツキ層を有したリード線を用
いても信頼性を損うことなく、高信頼性で安価な
半導体装置を提供できるその効果は大きい。
As explained above, according to the present invention, a highly reliable and inexpensive semiconductor device can be provided without impairing reliability even when a lead wire having a plating layer with a sufficient thickness for solder wettability is used. The effect is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の実施例を説明する半導体装置の
断面図である。第2図は本発明の一実施例の半導
体装置のリード線と電極の接続部近傍の断面図で
あり、第3図は本発明の他の実施例のリード線と
電極との接続部近傍の断面図である。 尚、図において、1,11,21……半導体素
子、2,12,22……電極、3,13,23…
…リード線、3′,13′,23′……メツキ層、
4……樹脂フイルム、5……金属粒塊、15,2
5……溶融、軟化した金属、6……開孔、7,1
7,27……凹部である。
FIG. 1 is a sectional view of a semiconductor device illustrating a conventional example. FIG. 2 is a sectional view of the vicinity of the connection between the lead wire and the electrode of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a sectional view of the vicinity of the connection between the lead wire and the electrode of another embodiment of the present invention. FIG. In the figure, 1, 11, 21... semiconductor element, 2, 12, 22... electrode, 3, 13, 23...
... Lead wire, 3', 13', 23'... Plating layer,
4...Resin film, 5...Metal granules, 15,2
5...Melted, softened metal, 6...Open hole, 7,1
7, 27... Concavity.

Claims (1)

【特許請求の範囲】[Claims] 1 複数個の電極を有する半導体素子と、該半導
体素子の電極にリードの先端部を圧着接続してな
る半導体装置において、前記リードの先端部には
前記電極に対向する位置から外れた近傍に該リー
ドを貫通しない凹部を設け、該凹部の表面をメツ
キ層で覆い、このメツキ層で覆われた前記凹部に
て接続時の熱によつて溶融もしくは軟化した金属
を表面張力によつて吸引することを特徴とする半
導体装置。
1. In a semiconductor device comprising a semiconductor element having a plurality of electrodes and a tip of a lead crimped and connected to the electrode of the semiconductor element, the tip of the lead has a contact point in the vicinity away from the position facing the electrode. A recess that does not penetrate the lead is provided, the surface of the recess is covered with a plating layer, and the metal melted or softened by the heat during connection is attracted by surface tension in the recess covered with the plating layer. A semiconductor device characterized by:
JP16487678A 1978-12-27 1978-12-27 Semiconductor device Granted JPS5591133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16487678A JPS5591133A (en) 1978-12-27 1978-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16487678A JPS5591133A (en) 1978-12-27 1978-12-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5591133A JPS5591133A (en) 1980-07-10
JPS6153853B2 true JPS6153853B2 (en) 1986-11-19

Family

ID=15801588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16487678A Granted JPS5591133A (en) 1978-12-27 1978-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5591133A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH052366U (en) * 1991-06-24 1993-01-14 富士電気化学株式会社 Cylindrical alkaline battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029218A (en) * 1983-07-14 1985-02-14 Oyo Jiki Kenkyusho:Kk Wire-cut machining method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128467U (en) * 1975-04-11 1976-10-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029218A (en) * 1983-07-14 1985-02-14 Oyo Jiki Kenkyusho:Kk Wire-cut machining method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH052366U (en) * 1991-06-24 1993-01-14 富士電気化学株式会社 Cylindrical alkaline battery

Also Published As

Publication number Publication date
JPS5591133A (en) 1980-07-10

Similar Documents

Publication Publication Date Title
US6164523A (en) Electronic component and method of manufacture
US7842889B2 (en) Substrate for mounting electronic part and electronic part
JP3201957B2 (en) Metal bump, method for manufacturing metal bump, connection structure
JP2000031204A (en) Manufacture of semiconductor package
US4042951A (en) Gold-germanium alloy contacts for a semiconductor device
JPH0378230A (en) Bump electrode for integrated circuit device
JPH04133330A (en) Semiconductor device and its connecting method
JP3171477B2 (en) Semiconductor device
GB2138633A (en) Bonding semiconductor chips to a lead frame
JPS6153853B2 (en)
EP0074378A1 (en) Semiconductor device including plateless package
JPH0590465A (en) Semiconductor device
JP2001094004A (en) Semiconductor device, external connecting terminal body structure and method for producing semiconductor device
WO2024142915A1 (en) Semiconductor device and method for manufacturing semiconductor device
KR100460075B1 (en) Method of forming diffusion barrier layer of semiconductor package
JP2848373B2 (en) Semiconductor device
JPH06260577A (en) Coating structure of wiring electrode
JPH04236469A (en) Method of forming solder bump for mounting superconducting integrated-circuit
JP3325804B2 (en) Semiconductor device and manufacturing method thereof
JPH05335309A (en) Semiconductor device
JP2911005B2 (en) Processing method of bump electrode
JPS6344991Y2 (en)
JPS61234043A (en) Semiconductor device
JPH1041358A (en) Tape carrier for semiconductor device
JPS6352461B2 (en)