JPS6153818A - 遅延回路 - Google Patents

遅延回路

Info

Publication number
JPS6153818A
JPS6153818A JP59174004A JP17400484A JPS6153818A JP S6153818 A JPS6153818 A JP S6153818A JP 59174004 A JP59174004 A JP 59174004A JP 17400484 A JP17400484 A JP 17400484A JP S6153818 A JPS6153818 A JP S6153818A
Authority
JP
Japan
Prior art keywords
potential
transistor
circuit
delay time
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59174004A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0354899B2 (enrdf_load_stackoverflow
Inventor
Shigeru Fujii
藤井　滋
Masanori Ozeki
大関　正徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59174004A priority Critical patent/JPS6153818A/ja
Priority to US06/767,574 priority patent/US4700089A/en
Priority to EP85306004A priority patent/EP0175501B1/en
Priority to DE8585306004T priority patent/DE3582640D1/de
Priority to KR8506104A priority patent/KR890004465B1/ko
Publication of JPS6153818A publication Critical patent/JPS6153818A/ja
Publication of JPH0354899B2 publication Critical patent/JPH0354899B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00215—Layout of the delay element using FET's where the conduction path of multiple FET's is in parallel or in series, all having the same gate control

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
JP59174004A 1984-08-23 1984-08-23 遅延回路 Granted JPS6153818A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP59174004A JPS6153818A (ja) 1984-08-23 1984-08-23 遅延回路
US06/767,574 US4700089A (en) 1984-08-23 1985-08-20 Delay circuit for gate-array LSI
EP85306004A EP0175501B1 (en) 1984-08-23 1985-08-23 Delay circuit for gate-array lsi
DE8585306004T DE3582640D1 (de) 1984-08-23 1985-08-23 Verzoegerungsschaltung fuer lsi-toranordnung.
KR8506104A KR890004465B1 (en) 1984-08-23 1985-08-23 Delay circuit for gate array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59174004A JPS6153818A (ja) 1984-08-23 1984-08-23 遅延回路

Publications (2)

Publication Number Publication Date
JPS6153818A true JPS6153818A (ja) 1986-03-17
JPH0354899B2 JPH0354899B2 (enrdf_load_stackoverflow) 1991-08-21

Family

ID=15970962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59174004A Granted JPS6153818A (ja) 1984-08-23 1984-08-23 遅延回路

Country Status (2)

Country Link
JP (1) JPS6153818A (enrdf_load_stackoverflow)
KR (1) KR890004465B1 (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382126A (ja) * 1986-09-26 1988-04-12 Sharp Corp バスレベル保持回路
JPS63119318A (ja) * 1986-11-07 1988-05-24 Hitachi Ltd 位相比較器
JPH01213023A (ja) * 1988-02-22 1989-08-25 Fujitsu Ltd 遅延回路
JPH04150612A (ja) * 1990-10-15 1992-05-25 Mitsubishi Electric Corp 半導体集積回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834619A (ja) * 1981-08-24 1983-03-01 Hitachi Ltd 波形整形回路
JPS5966218A (ja) * 1982-10-08 1984-04-14 Hitachi Micro Comput Eng Ltd 遅延回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834619A (ja) * 1981-08-24 1983-03-01 Hitachi Ltd 波形整形回路
JPS5966218A (ja) * 1982-10-08 1984-04-14 Hitachi Micro Comput Eng Ltd 遅延回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382126A (ja) * 1986-09-26 1988-04-12 Sharp Corp バスレベル保持回路
JPS63119318A (ja) * 1986-11-07 1988-05-24 Hitachi Ltd 位相比較器
JPH01213023A (ja) * 1988-02-22 1989-08-25 Fujitsu Ltd 遅延回路
JPH04150612A (ja) * 1990-10-15 1992-05-25 Mitsubishi Electric Corp 半導体集積回路

Also Published As

Publication number Publication date
KR870002660A (ko) 1987-04-06
JPH0354899B2 (enrdf_load_stackoverflow) 1991-08-21
KR890004465B1 (en) 1989-11-04

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term