JPS6152980B2 - - Google Patents
Info
- Publication number
- JPS6152980B2 JPS6152980B2 JP13048280A JP13048280A JPS6152980B2 JP S6152980 B2 JPS6152980 B2 JP S6152980B2 JP 13048280 A JP13048280 A JP 13048280A JP 13048280 A JP13048280 A JP 13048280A JP S6152980 B2 JPS6152980 B2 JP S6152980B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- cvd
- oxidation
- element region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 37
- 230000003647 oxidation Effects 0.000 claims description 21
- 238000007254 oxidation reaction Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- -1 oxygen ions Chemical class 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 229910052594 sapphire Inorganic materials 0.000 description 14
- 239000010980 sapphire Substances 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 6
- 241000293849 Cordylanthus Species 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000000386 microscopy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は絶縁体基板上に半導体層を設けた半導
体装置の製造方法に関し、特に半導体装置の信頼
性向上ならびに素子の微細化と集積度の向上に適
した製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor layer is provided on an insulating substrate, and in particular to a manufacturing method suitable for improving the reliability of semiconductor devices, miniaturizing elements, and increasing the degree of integration. Related.
この種の半導体装置における各素子は周囲を絶
縁された半導体領域（素子領域）に形成される。
例えばサフイア基板上にシリコン層を形成した
SOS構造（Silicon on Sapphire）の半導体装置
の場合、前記素子領域は例えば次のようにして形
成されている。 Each element in this type of semiconductor device is formed in a semiconductor region (element region) whose periphery is insulated.
For example, a silicon layer was formed on a sapphire substrate.
In the case of a semiconductor device having an SOS structure (Silicon on Sapphire), the element region is formed, for example, as follows.
即ち、サフアイア基板１１上に形成したシリコ
ン層の素子領域予定部上にパターンニングされた
CVD―SiO2膜１２を残置し、このCVD―SiO2膜
１２をマスクとした異方性エツチングによりフイ
ールド部分のシリコン層を選択的に除去して周囲
が空気絶縁された断面台形状の素子領域１３を形
成する（第１図Ａ図示）。 That is, the silicon layer formed on the sapphire substrate 11 is patterned on the intended device region.
The CVD-SiO 2 film 12 is left behind, and the silicon layer in the field portion is selectively removed by anisotropic etching using the CVD-SiO 2 film 12 as a mask to form an element region with a trapezoidal cross section whose surroundings are air-insulated. 13 (as shown in FIG. 1A).
こうして形成された素子領域１３を用いて半導
体装置を製造する場合、次のような問題が生じ
る。即ち、CVD―SiO2膜１２を除去し、素子領
域１３の表面を熱酸化してゲート酸化膜１５を形
成する場合、素子領域１３の側面が末広がりに傾
斜しているために、素子領域の下端部１６ではゲ
ート酸化膜１５が薄く形成される（第１図Ｂ図
示）。従つて同図Ｃに図示するように、ゲート酸
化膜１５上にゲート電極１７を形成して製造され
た半導体装置ではゲート耐圧が低下するという問
題があつた。また、フイールド部分のシリコン層
を全部除去しているためにサフアイア基板１１上
に各素子領域１３が突出して大きな段差を生じる
こととなり、この上に形成される各種の配線層が
その段差部分で断切れを起こし易く、従つて装置
の信頼性が低下するという問題があつた。 When manufacturing a semiconductor device using the element region 13 thus formed, the following problem occurs. That is, when removing the CVD-SiO 2 film 12 and thermally oxidizing the surface of the element region 13 to form the gate oxide film 15, the lower end of the element region In the portion 16, the gate oxide film 15 is formed thinly (as shown in FIG. 1B). Therefore, as shown in FIG. 2C, a semiconductor device manufactured by forming a gate electrode 17 on a gate oxide film 15 has a problem in that the gate breakdown voltage is lowered. In addition, since the silicon layer in the field portion is completely removed, each element region 13 protrudes on the sapphire substrate 11, resulting in a large step, and various wiring layers formed thereon are cut at the step. There was a problem that breakage was likely to occur, resulting in a decrease in the reliability of the device.
これに対して、所謂選択酸化法によつて素子領
域を形成する方法を採用すれば上述の問題を回避
することができる。この方法は次のとおりであ
る。即ち、サフアイア基板２１上に形成されたシ
リコン層２２の素子領域予定部上にのみパターン
ニングされたCVD―Si3N4膜２３を残置し、これ
をマスクとしてシリコン層２２に異方性エツチン
グを施してフイールド部分のシリコン層をその膜
厚方向に部分的に除去する（第２図Ａ図示）。 On the other hand, the above-mentioned problem can be avoided by adopting a method of forming the element region by a so-called selective oxidation method. The method is as follows. That is, the patterned CVD-Si 3 N 4 film 23 is left only on the intended device region of the silicon layer 22 formed on the sapphire substrate 21, and the silicon layer 22 is anisotropically etched using this as a mask. Then, the silicon layer in the field portion is partially removed in the film thickness direction (as shown in FIG. 2A).
次にCVD―Si3N4マスク２３を耐酸化性マスク
として選択酸化を行ない、フイールド酸化膜２２
２で周囲を絶縁された素子領域２２１を形成する
（同図Ｂ図示）。この場合、図示のようにフイール
ド領域は酸化によつて隆起し、素子領域とフイー
ルド領域はほぼ平坦に形成される。従つて、
CVD―Si3N4マスク２３を除去し、同図Ｃに示す
ようにゲート酸化膜２５およびゲート電極２７を
形成し、更にその上に図示しない配線層を形成し
て製造された半導体装置ではフイールド領域と素
子領域との間の平坦性が比較的維持されるから配
線の断切れによる信頼性の低下は防止でき、また
第１図Ｂ，Ｃについて述べたゲート耐圧の低下に
よる信頼性低下も生じることはない。しかし、次
のような別の問題がある。即ち、フイールド酸化
膜２２２を形成するための選択酸化には高温長時
間の加熱処理を要し、これによつて素子領域２２
２に結晶欠陥が発生する。また、サフアイア基板
２１から素子領域２２２へのアルミニウムのアウ
トデイフユージヨンも発生し、これらが所謂ドレ
ーンリーク電流を生じる原因となつて半導体装置
の信頼性が低下することになる。更に、アルミニ
ウムのアウトデイフユージヨンは基板濃度を変化
させ、しきい値電圧のばらつきをもたらすため歩
留りが低下する。また、選択酸化によつて形成さ
れるフイールド酸化膜２２２はCVD―Si3N4マス
ク２３の下部に食い込んで所謂バードビークを形
成するから、バードビークの食込み分だけ素子領
域が狭くなる。この現象は半導体装置における集
積度の向上を阻害する大きな要因となる。更に、
素子領域２２１を上から見れば末広がりに張り出
した側面部分は一定の幅を有し、この張り出した
側面部分が半導体装置を高密度化する上で障害に
なるという問題がある。例えば、シリコン層の膜
厚が0.7μｍで素子領域２２１の側面とサフアイ
ア基板２１とのなす角が約56゜の場合、末広がり
に張り出した側面部分の幅は略0.4μｍとなる。
近年における微細化されたMOS型トランジスタ
のチヤンネル幅は１μｍ程度であるから、素子領
域２２１の前記側面部分の張り出し幅はチヤンネ
ル幅の40％にもなり、両側の張り出し幅の合計は
チヤンネル幅の80％に達することになる。この実
情を考慮すれば、半導体装置を更に高密度化し、
集積度を向上する上で素子領域２２１における末
広がりに張り出した側面部分が大きな障害になる
ことが理解されよう。 Next, selective oxidation is performed using the CVD-Si 3 N 4 mask 23 as an oxidation-resistant mask, and the field oxide film 22 is
2 to form an element region 221 whose periphery is insulated (as shown in FIG. 2B). In this case, as shown in the figure, the field region is raised by oxidation, and the element region and the field region are formed substantially flat. Therefore,
In a semiconductor device manufactured by removing the CVD-Si 3 N 4 mask 23, forming a gate oxide film 25 and a gate electrode 27 as shown in FIG. Since the flatness between the region and the element region is relatively maintained, it is possible to prevent a decrease in reliability due to disconnection of wiring, and also a decrease in reliability due to a decrease in gate breakdown voltage as described in FIG. 1B and C. Never. However, there are other problems as follows. That is, selective oxidation to form the field oxide film 222 requires heat treatment at high temperature and for a long period of time.
2 , crystal defects occur. In addition, out-diffusion of aluminum from the sapphire substrate 21 to the element region 222 also occurs, which causes so-called drain leakage current and reduces the reliability of the semiconductor device. Furthermore, aluminum out-diffusion changes the substrate concentration, resulting in threshold voltage variations, thereby reducing yield. Furthermore, the field oxide film 222 formed by selective oxidation digs into the lower part of the CVD-Si 3 N 4 mask 23 and forms a so-called bird's beak, so the device area becomes narrower by the amount of the bird's beak. This phenomenon becomes a major factor that hinders the improvement in the degree of integration in semiconductor devices. Furthermore,
When the element region 221 is viewed from above, the side surface portion that extends toward the end has a certain width, and there is a problem in that this projecting side surface portion becomes an obstacle to increasing the density of the semiconductor device. For example, when the thickness of the silicon layer is 0.7 μm and the angle between the side surface of the element region 221 and the sapphire substrate 21 is approximately 56°, the width of the side surface portion that extends toward the end is approximately 0.4 μm.
Since the channel width of recent miniaturized MOS transistors is about 1 μm, the overhang width of the side portion of the element region 221 is as much as 40% of the channel width, and the sum of the overhang widths on both sides is equal to the channel width. It will reach 80%. Taking this fact into consideration, it is necessary to further increase the density of semiconductor devices,
It will be understood that the side portions of the element region 221 that extend toward the end become a major obstacle in improving the degree of integration.
本発明は上述の事情に鑑みてなされたものであ
り、選択酸化法によつて素子領域を形成する方法
を改良することにより配線の断切れおよびゲート
耐圧の低下を防止しつつ選択酸化法に伴うバード
ビークの形成ならびにドレインリーク電流の発
生、しきい値電圧のばらつきを極力抑制して信頼
性の高い半導体装置を高歩留りで得ることがで
き、かつ装置の高密度化に適した半導体装置の製
造方法を提供するものである。 The present invention has been made in view of the above-mentioned circumstances, and by improving the method of forming element regions by selective oxidation, it is possible to prevent disconnection of wiring and decrease in gate withstand voltage, and to avoid the problems associated with selective oxidation. A method for manufacturing a semiconductor device that can obtain highly reliable semiconductor devices at a high yield by minimizing the formation of bird beaks, drain leakage current, and variations in threshold voltage, and is suitable for increasing the density of devices. It provides:
即ち、本発明による半導体装置の製造方法は、
絶縁体基板上に形成された半導体層の素子領域予
定部上にパターンニングされた耐酸化性膜を形成
する工程と、この耐酸化性膜をマスクとした異方
性エツチングによりフイールド部分の半導体層を
その膜厚方向に部分的に除去する工程と、前記耐
酸化性膜をマスクとして半導体層に酸素をイオン
注入する工程と、これを加熱処理して半導体層の
酸素注入領域を絶縁物層に転化してフイールド領
域を形成する工程とを具備したことを特徴とする
ものである。 That is, the method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor layer in the field portion is formed by forming a patterned oxidation-resistant film on the intended device region of the semiconductor layer formed on the insulating substrate, and by anisotropic etching using this oxidation-resistant film as a mask. a step of partially removing the oxidation-resistant film in the direction of its film thickness, a step of implanting oxygen ions into the semiconductor layer using the oxidation-resistant film as a mask, and a heat treatment to transform the oxygen-implanted region of the semiconductor layer into an insulating layer. The present invention is characterized by comprising a step of converting the material into a field region to form a field region.
本発明における絶縁体基板としてはサフアイア
基板の他、スピネル基板、ガーネツト基板等の絶
縁体基板を用いることができる。また、半導体層
としてはシリコン、ゲルマニウム、ガリウム―砒
素等の半導体層を用いることができる。 As the insulating substrate in the present invention, other than sapphire substrates, insulating substrates such as spinel substrates and garnet substrates can be used. Further, as the semiconductor layer, a semiconductor layer of silicon, germanium, gallium-arsenic, etc. can be used.
本発明における耐酸化性膜としては窒化膜を用
いることができる。これを単独で用いてもよい
が、後続の加熱処理によつて素子領域が窒素で汚
染されるのを防止するために、半導体層との間に
酸化膜を介在させて用いるのが好ましい。 A nitride film can be used as the oxidation-resistant film in the present invention. Although this may be used alone, it is preferable to use it with an oxide film interposed between it and the semiconductor layer in order to prevent the element region from being contaminated with nitrogen during subsequent heat treatment.
本発明における異方性エツチングはヒドラジン
液、KOH液あるいはプラズマエツチングなどを
用いた異方性エツチングにより行なうことができ
る。 The anisotropic etching in the present invention can be carried out using a hydrazine solution, a KOH solution, or plasma etching.
本発明における酸素のイオン注入は、注入され
た酸素の濃度ピークがシリコン層とサフアイア基
板の界面付近にくるように加速電圧を調整し、ピ
ーク位置での酸素濃度が1019／cm3以上になるよう
にドーズ量を調整して行なう。また、酸素イオン
の注入ピーク位置をシリコン層の膜厚方向に移動
させた多段イオン注入を行なうのも好ましい。 In the ion implantation of oxygen in the present invention, the acceleration voltage is adjusted so that the concentration peak of the implanted oxygen is near the interface between the silicon layer and the sapphire substrate, and the oxygen concentration at the peak position is 10 19 /cm 3 or more. Adjust the dose accordingly. It is also preferable to perform multistage ion implantation in which the implantation peak position of oxygen ions is moved in the thickness direction of the silicon layer.
本発明における加熱処理は酸化性雰囲気下で行
なつてもよく、また、N2，Arその他の不活性ガ
ス等、非酸化性雰囲気下で行なつてもよい。特に
非酸化性雰囲気下で加熱処理を行えば、バードビ
ークの発生を略完全に抑制することができる。 The heat treatment in the present invention may be carried out under an oxidizing atmosphere, or may be carried out under a non-oxidizing atmosphere such as N 2 , Ar or other inert gas. In particular, if the heat treatment is performed in a non-oxidizing atmosphere, the occurrence of bird's beak can be almost completely suppressed.
以下本発明をSOS構造の半導体装置の製造に適
用した１実施例につき、第３図Ａ〜Ｅを参照して
説明する。 An embodiment in which the present invention is applied to the manufacture of a semiconductor device having an SOS structure will be described below with reference to FIGS. 3A to 3E.
〔〕 まず、サフアイア基板３１上に膜厚0.7μ
ｍのシリコン層３２をエピタキシヤル成長さ
せ、その上にCVD法によつてSiO2膜３３を堆
積し、更にその上にCVD法によつてSi3N4膜３
４を堆積した（第３図Ａ図示）。[] First, a film with a thickness of 0.7μ is deposited on the sapphire substrate 31.
m silicon layer 32 is epitaxially grown, a SiO 2 film 33 is deposited on it by CVD method, and a Si 3 N 4 film 3 is deposited on it by CVD method.
4 was deposited (as shown in FIG. 3A).
〔〕 次に、写真蝕刻法によつてCVD―SiO2膜
３３およびCVD―Si3N4膜３４をパターンニン
グし、シリコン層３２の素子領域予定部上にの
みCVD―SiO2膜３３およびCVD―Si3N4膜３４
を残置する。続いて残置されたCVD―SiO2膜
３３およびCVD―Si3N4膜３４をマスクとして
KOH液による異方性エツチングを行ない、フ
イールド部分のシリコン層３２をその膜厚方向
に部分的に除去する（同図Ｂ図示）。[] Next, the CVD-SiO 2 film 33 and the CVD-Si 3 N 4 film 34 are patterned by photolithography, and the CVD-SiO 2 film 33 and the CVD-SiO 2 film 34 are formed only on the intended device region of the silicon layer 32. -Si 3 N 4 film 34
remain. Next, the remaining CVD-SiO 2 film 33 and CVD-Si 3 N 4 film 34 were used as a mask.
Anisotropic etching is performed using a KOH solution to partially remove the silicon layer 32 in the field portion in the direction of its film thickness (as shown in Figure B).
〔〕 次に、残置されたCVD―SiO2膜３３およ
びCVD―Si3N4膜３４をマスクとして酸素を加
速電圧250keV、ドーズ量１×1018／cm2の条件
でイオン注入し、フイールド領域に酸素注入層
３２′，３２′を形成する（同図Ｃ図示）。[] Next, using the remaining CVD-SiO 2 film 33 and CVD-Si 3 N 4 film 34 as masks, oxygen ions were implanted at an acceleration voltage of 250 keV and a dose of 1×10 18 /cm 2 to form the field region. Oxygen implantation layers 32', 32' are formed (as shown in C in the same figure).
〔〕 次に、CVD―Si3N4膜３４を耐酸化性マ
スクとして非酸化性雰囲気下で900℃、10時間
の加熱処理を行ない、フイールド酸化膜３２２
を形成した。この際、フイールド酸化膜３２２
は隆起して素子領域３２１との段差が解消さ
れ、素子領域表面とフイールド酸化膜表面とは
略平坦に形成される（同図Ｄ図示）。[] Next, heat treatment is performed at 900°C for 10 hours in a non-oxidizing atmosphere using the CVD-Si 3 N 4 film 34 as an oxidation-resistant mask, and the field oxide film 32 2
was formed. At this time, the field oxide film 32 2
is raised to eliminate the level difference with the element region 321 , and the surface of the element region and the surface of the field oxide film are formed substantially flat (as shown in figure D).
この段階でシリコン層断面のSEM観察
（Scanning EIectron Microscopy）を行なつた
ところ、図示のように素子領域３２１の側面は
サフアイア基板３１に対して略垂直に形成され
ていることがわかつた。 At this stage, SEM observation (Scanning EIectron Microscopy) of the cross section of the silicon layer revealed that the side surfaces of the element region 321 were formed substantially perpendicular to the sapphire substrate 31 as shown in the figure.
〔〕 次に、CVD―SiO2膜３３およびCVD―
Si3N4膜３４を除去し、素子領域３２１の表面
を熱酸化してゲート酸化膜３５を形成し、続い
てその上に多結晶シリコンからなるゲート電極
３６をパターンニング形成した後、該ゲート電
極３６をマスクとしてこれに自己整合でソース
領域およびドレイン領域を形成して半導体装置
を製造した（同図Ｅ図示）。[] Next, CVD-SiO 2 film 33 and CVD-
After removing the Si 3 N 4 film 34 and thermally oxidizing the surface of the element region 321 to form a gate oxide film 35, a gate electrode 36 made of polycrystalline silicon is formed thereon by patterning. A semiconductor device was manufactured by forming a source region and a drain region in self-alignment using the gate electrode 36 as a mask (as shown in Figure E).
上記実施例の方法によれば、フイールド領域と
素子領域との間の誤差による配線の断切れおよび
ゲート耐圧の低下という問題を回避でき、かつ選
択酸化法に伴う種々の問題を解決することができ
る。 According to the method of the above embodiment, it is possible to avoid the problems of wiring disconnection and reduction in gate breakdown voltage due to errors between the field region and the element region, and it is also possible to solve various problems associated with the selective oxidation method. .
即ちフイールド酸化に先立つてフイールド部分
に酸素がイオン注入されているため、酸化時間が
通常の選択酸化法に比較して短かくてすむ。従つ
て素子領域３２１における結晶欠陥の発生および
サフアイア基板３１からのアルミニウムのアウト
デイフユージヨンを抑制してドレインリーク電流
の発生を防止し、しきい値電圧のばらつきを抑制
することができる。また、バードビークの形成を
防止し、更に、素子領域３２１の側面をサフアイ
ア基板３１に垂直に形成できるから、素子の高密
度化を達成して半導体装置の集積度を向上させる
ことが可能となる。 That is, since oxygen ions are implanted into the field portion prior to field oxidation, the oxidation time is shorter than in the normal selective oxidation method. Therefore, generation of crystal defects in the element region 321 and out-diffusion of aluminum from the sapphire substrate 31 can be suppressed, drain leakage current can be prevented, and variations in threshold voltage can be suppressed. Furthermore, since the formation of bird's beaks can be prevented and the side surfaces of the element regions 321 can be formed perpendicular to the sapphire substrate 31, it is possible to achieve higher density of elements and improve the degree of integration of semiconductor devices. .
なお、上記実施例ではMOS型半導体装置につ
いて述べたが、本発明はバイポーラ型の半導体装
置にも適用することができる。 In the above embodiments, a MOS type semiconductor device has been described, but the present invention can also be applied to a bipolar type semiconductor device.
以上詳述したように、本発明によれば配線の断
切れおよびゲート耐圧の低下を回避し、またドレ
インリーク電流の発生等を防止し得、かつ素子の
微細化と高密度化に適した半導体装置の製造方法
を提供できるものである。 As described in detail above, according to the present invention, it is possible to avoid disconnection of wiring and a reduction in gate breakdown voltage, prevent the occurrence of drain leakage current, etc., and make the semiconductor suitable for miniaturization and high density of elements. A method for manufacturing the device can be provided.
第１図Ａ〜Ｃは従来法による半導体装置の製造
工程を示す断面図、第２図Ａ〜Ｃは別の従来法に
よる半導体装置の製造工程を示す断面図、第３図
Ａ〜Ｅは本発明による半導体装置の製造工程の１
実施例を示す断面図である。
３１…サフアイア基板、３２…シリコン層、３
３…CVD―SiO2膜、３４…CVD―Si3N4膜、３５
…ゲート酸化膜、３６…ゲート電極、３２１…素
子領域、３２２…フイールド酸化膜。
1A to 1C are cross-sectional views showing the manufacturing process of a semiconductor device using a conventional method, FIGS. 2A to 2C are sectional views showing the manufacturing process of a semiconductor device using another conventional method, and FIGS. 1 of the manufacturing process of the semiconductor device according to the invention
It is a sectional view showing an example. 31...Sapphire substrate, 32...Silicon layer, 3
3...CVD-SiO 2 film, 34...CVD-Si 3 N 4 film, 35
...Gate oxide film, 36...Gate electrode, 32 1 ...Element region, 32 2 ...Field oxide film.
Claims (1)
域予定部上にパターンニングされた耐酸化性膜を
形成する工程と、この耐酸化性膜をマスクとした
異方性エツチングによりフイールド領域予定部の
半導体層をその膜厚方向に部分的に除去する工程
と、前記耐酸化性膜をマスクとして半導体層に酸
素をイオン注入する工程と、これを加熱処理して
半導体層の酸素注入領域を絶縁物層に転化してフ
イールド領域を形成する工程とを具備したことを
特徴とする半導体装置の製造方法。1 Step of forming a patterned oxidation-resistant film on the intended element region of a semiconductor layer formed on an insulating substrate, and anisotropic etching using this oxidation-resistant film as a mask to form the intended field region. a step of partially removing the semiconductor layer in the film thickness direction; a step of implanting oxygen ions into the semiconductor layer using the oxidation-resistant film as a mask; and heat-treating this to insulate the oxygen-implanted region of the semiconductor layer. 1. A method of manufacturing a semiconductor device, comprising the step of converting the material into a physical layer to form a field region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13048280A JPS5754342A (en) | 1980-09-19 | 1980-09-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13048280A JPS5754342A (en) | 1980-09-19 | 1980-09-19 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5754342A JPS5754342A (en) | 1982-03-31 |
| JPS6152980B2 true JPS6152980B2 (en) | 1986-11-15 |
Family
ID=15035303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13048280A Granted JPS5754342A (en) | 1980-09-19 | 1980-09-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5754342A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58175842A (en) * | 1982-04-08 | 1983-10-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH09129630A (en) * | 1995-09-20 | 1997-05-16 | Lucent Technol Inc | Manufacture of integrated circuit |
-
1980
- 1980-09-19 JP JP13048280A patent/JPS5754342A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5754342A (en) | 1982-03-31 |
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