JPS6152397U - - Google Patents
Info
- Publication number
- JPS6152397U JPS6152397U JP13728284U JP13728284U JPS6152397U JP S6152397 U JPS6152397 U JP S6152397U JP 13728284 U JP13728284 U JP 13728284U JP 13728284 U JP13728284 U JP 13728284U JP S6152397 U JPS6152397 U JP S6152397U
- Authority
- JP
- Japan
- Prior art keywords
- bit
- latches
- memory circuit
- memory
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の実施例のブロツク図、第２図
は第１図におけるタイムチヤート、第３図は従来
のメモリー回路のブロツク図、第４図は第３図に
おけるタイムチヤートである。
１１：スイツチ、１２〜１７：書き込みラツチ
、１８〜２２：メモリ、２３〜２７：ラツチ。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart in FIG. 1, FIG. 3 is a block diagram of a conventional memory circuit, and FIG. 4 is a time chart in FIG. 3. 11: switch, 12-17: write latch, 18-22: memory, 23-27: latch.
Claims (1)
データを順次前記クロツクでラツチするｎ個のラ
ツチとを備え、それぞれのラツチ出力を並列にメ
モリーに書き込むメモリー回路において、少くと
も前記各ラツチの入力側又は出力側にそれぞれｍ
ｂｉｔ，ｍ−１ｂｉｔ，……，１ｂｉｔ遅延させ
る手段を備えることを特徴とするメモリー回路（
但し、ｍ，ｎ：自然数でｍ＜ｎとする）。 In a memory circuit comprising n clock generating means of different phases and n latches for sequentially latching input data with the clock, and writing the outputs of the respective latches to the memory in parallel, at least the input side of each of the latches. or m each on the output side
A memory circuit characterized by comprising means for delaying bit, m-1 bit, ..., 1 bit (
However, m, n: natural numbers, m<n).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13728284U JPS6152397U (en) | 1984-09-12 | 1984-09-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13728284U JPS6152397U (en) | 1984-09-12 | 1984-09-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6152397U true JPS6152397U (en) | 1986-04-08 |
Family
ID=30695697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13728284U Pending JPS6152397U (en) | 1984-09-12 | 1984-09-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6152397U (en) |
-
1984
- 1984-09-12 JP JP13728284U patent/JPS6152397U/ja active Pending
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