JPS6150381B2 - - Google Patents
Info
- Publication number
- JPS6150381B2 JPS6150381B2 JP54027479A JP2747979A JPS6150381B2 JP S6150381 B2 JPS6150381 B2 JP S6150381B2 JP 54027479 A JP54027479 A JP 54027479A JP 2747979 A JP2747979 A JP 2747979A JP S6150381 B2 JPS6150381 B2 JP S6150381B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- capillary
- wire
- chip
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 8
- 238000004070 electrodeposition Methods 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 6
- 230000005856 abnormality Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【発明の詳細な説明】
本発明は半導体チツプ上の電極とリードフレー
ムとの間が金属の極細線で電気的接続されるワイ
ヤボンデイングの改良に関するもので、特に自動
ワイヤボンデイング工程中におけるキヤピラリイ
の保護を図つたものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in wire bonding in which electrodes on a semiconductor chip and a lead frame are electrically connected using ultrafine metal wires, and in particular to protection of capillaries during automatic wire bonding processes. This is what we are trying to achieve.
近年半導体装置製造の自動化が頻繁に試みら
れ、特に半導体チツプ上の電極にワイヤをボンデ
イングする工程は完全自動化された装置が開発さ
れている。 In recent years, attempts have been made frequently to automate the manufacturing of semiconductor devices, and in particular, fully automated equipment has been developed for the process of bonding wires to electrodes on semiconductor chips.
半導体チツプ電極にワイヤがボンデイングされ
る場合、ワイヤは極めて細い線が用いられるため
形状が不安定で、わずかの外力が加えられた状態
でも変形や断線を招く惧れがある。そのため従来
からこの種の装置においては、中央部にワイヤガ
イド孔が穿設されたキヤピラリイからワイヤが導
出されてボンデイング部に供給されている。ボン
デイング作業時にはワイヤ先端を突出させたキヤ
ピラリイを半導体チツプ電極等の所望ボンデイン
グ位置に押圧させることによつてワイヤと電極と
の接続がなされる。しかしこのようなボンデイン
グ工程において、ワイヤが所望位置に且つ堅固に
接着されるためにはボンデイング部に押圧される
キヤピラリイ先端部を常に損傷のない、また異物
が付着していない適正な状態に維持されることが
何にも増して重要なことである。 When wires are bonded to semiconductor chip electrodes, the wires used are extremely thin and therefore have an unstable shape, and there is a risk of deformation or disconnection even when a slight external force is applied. Conventionally, therefore, in this type of device, a wire is led out from a capillary having a wire guide hole bored in the center and supplied to a bonding section. During bonding work, the wire and electrode are connected by pressing a capillary with a protruding wire tip onto a desired bonding position such as a semiconductor chip electrode. However, in such a bonding process, in order for the wire to be firmly bonded at the desired position, the tip of the capillary that is pressed against the bonding part must always be maintained in an appropriate state without damage or foreign matter. It is more important than anything else.
ボンデイング作業時にキヤピラリイ先端に損傷
を与えるような場合として、次のような事態があ
る。 The following situations can cause damage to the capillary tip during bonding work.
(a) キヤピラリイによつてワイヤ端を半導体チツ
プ電極に押圧した際、半導体チツプをリードフ
レームにダイボンドさせている接着力が不充分
等のために、キヤピラリイを持ち上げて移動さ
せる過程でチツプがリードフレームから剥れ、
チツプを付着させたままキヤピラリイが次のボ
ンデイング位置に位置調整される。(a) When the wire end is pressed against the semiconductor chip electrode by the capillary, the adhesive force that binds the semiconductor chip to the lead frame is insufficient, so the chip is attached to the lead frame during the process of lifting and moving the capillary. peels off,
The capillary is adjusted to the next bonding position with the chip still attached.
(b) 半導体チツプ電極へキヤピラリイを押圧して
ワイヤ端を接着させた際、チツプ或いは電極の
一部が剥離してワイヤ端に付着し、そのままの
状態でキヤピラリイが次のボンデイング位置に
位置調整される。(b) When pressing the capillary against the semiconductor chip electrode and bonding the wire end, part of the chip or electrode peels off and adheres to the wire end, and the capillary is adjusted to the next bonding position in that state. Ru.
上記a及びbのようにキヤピラリイ先端に異常
を伴う場合には作業を中止して障害を取り除く必
要がある。 If there is an abnormality at the tip of the capillary as in a and b above, it is necessary to stop the work and remove the obstruction.
一方ワイヤボンデイングが正常になされていな
い状態としては、いわゆるワイヤ断線による場合
もある。このワイヤ断線による場合はキヤピラリ
イ先端に特に異常を伴うものではなく、従つてボ
ンデイング作業を継続させても特に障害になるも
のではなく、その都度作業を中断させていたので
は極めて不経済で、自動化させたことの意味が著
しく減少する。 On the other hand, a state in which wire bonding is not performed normally may be due to so-called wire breakage. In the case of this wire breakage, there is no particular abnormality at the tip of the capillary, and therefore it does not pose a particular problem even if the bonding work is continued, and it would be extremely uneconomical to interrupt the work each time, so automation The meaning of what was done is significantly diminished.
本発明は上記従来のワイヤボンデイング方式に
おける問題点に鑑みてなされたもので、キヤピラ
リイ先端に異常を伴うような事態を判別してその
後のボンデイング作業の継続を制御するものであ
る。 The present invention has been made in view of the problems in the conventional wire bonding method described above, and is intended to determine a situation in which an abnormality occurs at the tip of a capillary and to control the continuation of the bonding operation thereafter.
次に実施例を挙げて本発明を詳細に説明する。 Next, the present invention will be explained in detail with reference to Examples.
まず本発明の原理を説明する。 First, the principle of the present invention will be explained.
上述のa及びbの如くキヤピラリイ先端に損傷
を与える惧れのある場合はキヤピラリイが電極に
押圧された後、キヤピラリイを次のボンデイング
位置に移動させた状態で、aの場合は元のリード
フレームに半導体チツプが無く、またbの場合は
キヤピラリイ押圧後のチツプ表面がボンデイング
前の半導体チツプ表面像から著しく変化してお
り、いずれにしてもボンデイング前の半導体チツ
プ表面とは明らかに判別できる。例えば、周知の
ごとく、半導体チツプを数10μ単位の小さい矩形
に分解し、各セクシヨンにおける上からの照射光
の反射光をITVカメラ等により取り込んで、ある
一定レベル以上の映像信号を、半導体チツプの存
在するものとしてカウントする。このとき、半導
体チツプの剥れやチツプ表面に著しい変化が生じ
れば、上からの照射光は乱反射してカメラには返
らず、カウント数は減少する。従つて本発明にお
いては、ボンデイング前に電極位置を認識するた
めに予め撮像された半導体チツプ映像を利用し
て、ボンデイング後に再び同領域を撮像して両映
像を比較し、該比較結果に基いて次のキヤピラリ
イのボンデイング動作を制御する。 If there is a risk of damaging the tip of the capillary as in a and b above, after the capillary is pressed against the electrode, move the capillary to the next bonding position, and in case a, return to the original lead frame. There is no semiconductor chip, and in case b, the chip surface after capillary pressing has changed significantly from the semiconductor chip surface image before bonding, and in any case can be clearly distinguished from the semiconductor chip surface before bonding. For example, as is well known, a semiconductor chip is broken down into small rectangles of several tens of micrometers, and the reflected light from above in each section is captured by an ITV camera, etc., and a video signal of a certain level or higher is transmitted to the semiconductor chip. Count as existing. At this time, if the semiconductor chip peels off or a significant change occurs on the chip surface, the light irradiated from above will be diffusely reflected and will not return to the camera, resulting in a decrease in the number of counts. Therefore, in the present invention, an image of the semiconductor chip that has been previously imaged is used to recognize the electrode position before bonding, and after bonding, the same area is imaged again and the two images are compared, and based on the comparison result. Controls the bonding operation of the next capillary.
第1図に於て、1は先端頂部に半導体チツプ2
を搭載したリードフレームで、該リードフレーム
1は金属板が打抜き加工されて成型され、同一金
属板に複数のリード対が繰返しパターンで一体的
に設けられている。リード対の一方のリード線先
端に半導体チツプ2が導電性ペースト等で固着さ
れ、該半導体チツプ上の電極とリード対の他方の
リード線との間がボンデイング装置でワイヤボン
ドされる。半導体チツプ2がダイボンドされたリ
ードフレーム1はボンデイング装置のリードフレ
ーム送り機構に装着され、ボンデイング動作に同
期して一定ピツチで搬送され、ボンデイング作業
位置に順次送られる。ボンデイング作業位置には
装着されたリードフレーム及び半導体チツプ2表
面の映像を取り込むためのITVカメラ3が設置さ
れている。該ITVカメラ3に取付けられた光学系
には更に撮像時に撮像領域を照明する光源が設け
られている。また上記ITVカメラ3には映像処理
回路4及び該映像処理回路で処理された信号を記
憶するメモリ装置5が接続されている。該映像処
理回路4及びメモリ装置5には両者から出力され
る映像信号を比較するための比較回路6が接続さ
れて比較結果が制御装置7に転送され、ボンデイ
ング動作制御のための指令信号が形成される。上
記制御装置7はボンデイング装置の動作を制御す
るための各種制御信号を出力し、上記映像処理回
路4、メモリ装置5及び後述するキヤピラリイ8
の動作を制御する。キヤピラリイ8はワイヤ9を
順次繰り出してワイヤ9の先端を半動体チツプの
電極に押圧ボンデイングし、次に移動して同ワイ
ヤ9の他端を近接する他方のリードに押圧ボンデ
イングさせて、リード線と半導体チツプが電気的
接続された半導体装置を得る。 In Figure 1, 1 is a semiconductor chip 2 on the top of the tip.
The lead frame 1 is formed by punching a metal plate, and a plurality of lead pairs are integrally provided in a repeating pattern on the same metal plate. A semiconductor chip 2 is fixed to the tip of one of the lead wires of the lead pair using a conductive paste or the like, and wire bonding is performed between the electrode on the semiconductor chip and the other lead wire of the lead pair using a bonding device. The lead frame 1 to which the semiconductor chip 2 is die-bonded is mounted on a lead frame transport mechanism of a bonding apparatus, and is transported at a constant pitch in synchronization with the bonding operation, and is sequentially transported to a bonding work position. An ITV camera 3 is installed at the bonding work position to capture images of the mounted lead frame and the surface of the semiconductor chip 2. The optical system attached to the ITV camera 3 is further provided with a light source that illuminates the imaging area during imaging. Also connected to the ITV camera 3 is a video processing circuit 4 and a memory device 5 for storing signals processed by the video processing circuit. A comparison circuit 6 is connected to the video processing circuit 4 and the memory device 5 to compare the video signals outputted from both, and the comparison result is transferred to the control device 7 to form a command signal for controlling the bonding operation. be done. The control device 7 outputs various control signals for controlling the operation of the bonding device, and controls the video processing circuit 4, the memory device 5, and the capillary 8 described later.
control the behavior of The capillary 8 sequentially feeds out the wire 9 and press-bonds the tip of the wire 9 to the electrode of the semi-moving chip, and then moves and press-bonds the other end of the wire 9 to the other lead in the vicinity, thereby forming a lead wire. A semiconductor device in which semiconductor chips are electrically connected is obtained.
上記ワイヤボンデイング装置において、ボンデ
イング位置に搬送されたリードフレーム1は、ま
ず半導体チツプ2面がカメラ3で撮し出されて映
像処理回路4に転送され、適宜増幅等の処理が施
こされる。増幅処理された映像信号はメモリ装置
5に転送されて後述する比較のための一方の信号
になると共に、制御装置7にも与えられて予め設
定されたスライスレベルとの比較等によつて電極
位置情報が形成され、該電極位置情報からキヤピ
ラリイ8の変位量が算出され、キヤピラリイ駆動
機構を駆動させてキヤピラリイ8のワイヤ供給先
端をチツプ電極位置に対向させる。所定位置に対
向した状態でキヤピラリイ8がチツプ電極に押圧
され、ワイヤ9の一端がまず電極に第1ボンデイ
ングされる。次に制御装置7からの指令によつて
キヤピラリイ8は対をなすリード線の内の他方の
リード線と対向する位置まで距離lだけ、直線状
に或いは迂回して移動し、第2のボンデイングの
ための位置調整がなされる。 In the above-mentioned wire bonding apparatus, the lead frame 1 is transported to the bonding position, and the two sides of the semiconductor chip are first photographed by the camera 3 and transferred to the image processing circuit 4, where they are subjected to processing such as amplification as appropriate. The amplified video signal is transferred to the memory device 5 and becomes one signal for comparison, which will be described later, and is also provided to the control device 7 to determine the electrode position by comparison with a preset slice level, etc. Information is formed, the amount of displacement of the capillary 8 is calculated from the electrode position information, and the capillary drive mechanism is driven to cause the wire feeding tip of the capillary 8 to face the tip electrode position. The capillary 8 is pressed against the chip electrode while facing a predetermined position, and one end of the wire 9 is first bonded to the electrode. Next, in response to a command from the control device 7, the capillary 8 is moved linearly or in a detour by a distance l to a position opposite to the other of the pair of lead wires, and the second bonding The position will be adjusted accordingly.
ここで本発明においては、第1ボンデイングが
なされた後第2ボンデイングのためのキヤピラリ
イ8が位置調整される期間を利用して、第1ボン
デイング後のリードフレーム、特に半導体チツプ
2面の映像がカメラ3を介して再び取り込まれて
第1ボンデイング過程と同様に増幅等の処理が施
こされる。再撮像によつて得られた映像信号処理
回路4の出力は比較回路6に出力され、同時にメ
モリ装置5に収納されていたボンデイング前の映
像信号が比較回路6に与えられて両信号が比較さ
れる。例えば、映像信号がある一定レベル以上を
論理値“1”として2値化されるものとすると、
半導体チツプ2の存在する部分は論理値“1”
に、半導体チツプ2の存在しない部分或いはカケ
部分等においては論理値”0”に論理化される。
従つて、このような論理値“1”又は“0”とな
るセクシヨンの数をカウントして、ボンデイング
前に予め取り入れたチツプ部分のカウント数と第
1ボンデイング後のチツプ部分のカウント数の差
を取ると、チツプのハガレ又は一部欠損等を検出
することが可能となる。 In the present invention, after the first bonding is performed, the position of the capillary 8 for the second bonding is adjusted, so that the image of the lead frame, especially the second side of the semiconductor chip, after the first bonding is captured by the camera. 3 and subjected to processing such as amplification in the same manner as in the first bonding process. The output of the video signal processing circuit 4 obtained by re-imaging is sent to the comparison circuit 6, and at the same time, the video signal before bonding stored in the memory device 5 is given to the comparison circuit 6 and both signals are compared. Ru. For example, if a video signal is to be binarized with a logic value of "1" when it is above a certain level,
The part where semiconductor chip 2 exists has a logical value of “1”
In addition, the logic value is set to "0" in a portion where the semiconductor chip 2 does not exist or a chipped portion.
Therefore, the number of sections that have such a logical value of "1" or "0" is counted, and the difference between the count number of the chip part taken in advance before bonding and the count number of the chip part after the first bonding is calculated. When removed, it becomes possible to detect peeling or partial loss of the chip.
上記第1ボンデイングが適正に実行されている
状態ではボンデイング後といえどもワイヤ像が追
加される程度で両信号間に大きな差は生じない。
しかしながら、半導体チツプ全体がリードフレー
ムから離脱したり電極の一部等が剥離した場合に
は両信号間に差が発生し、比較回路6から両信号
間に差が発生していることが出力され、異常状態
と認識して制御装置7からボンデイング作業停止
を指令すると共に異常を報知する。 When the first bonding is properly performed, even after bonding, only a wire image is added and there is no significant difference between the two signals.
However, if the entire semiconductor chip is detached from the lead frame or a part of the electrode is peeled off, a difference will occur between the two signals, and the comparison circuit 6 will output that there is a difference between the two signals. , recognizes the abnormal state and issues a command to stop the bonding work from the control device 7, as well as notifying the abnormal state.
尚第1ボンデイングに異常のないことが認識さ
れた状態で、既に第2ボンデイングのために位置
調整されているキヤピラリイ8が他方のリード線
に押圧され、ワイヤ9の他端がリード線にボンデ
イングされて、半導体チツプ2とリードフレーム
間がワイヤボンデイングされた構造を得る。 When it is recognized that there is no abnormality in the first bonding, the capillary 8 whose position has already been adjusted for the second bonding is pressed against the other lead wire, and the other end of the wire 9 is bonded to the lead wire. Thus, a structure in which the semiconductor chip 2 and the lead frame are wire bonded is obtained.
以上本発明のように、ボンデイング位置を認識
するためにボデイング前に取り込まれた半導体チ
ツプの映像信号を予め記憶させ、ボンデイング後
に再び同領域を撮像装置によつて撮し出し、記憶
させたボンデイング前のチップ映像とボンデイン
グ後の映像を比較させて出力を形成し、該比較結
果によつて第1ボンデイング作業時に異常が発生
していると認識されればボンデイング作業を停止
させ、比較結果に異常がなければボンデイングが
適切に実行されたものとして動作を実行させるこ
とにより、自動化されたボンデイング装置のキヤ
ピラリイを損傷から防いで装置の保護を図ると共
に、半導体装置におけるワイヤボンデイングの信
頼性を高めることができる。 As described above, according to the present invention, in order to recognize the bonding position, the video signal of the semiconductor chip captured before bodying is stored in advance, and after bonding, the same area is photographed again by the imaging device and stored. The chip image is compared with the image after bonding to form an output, and if it is recognized from the comparison result that an abnormality has occurred during the first bonding operation, the bonding operation is stopped and the comparison result shows an abnormality. By performing the operation assuming that the bonding has been carried out properly, it is possible to prevent the capillary of automated bonding equipment from being damaged and protect the equipment, as well as to improve the reliability of wire bonding in semiconductor devices. .
図は本発明による実施例のブロツク図である。
1:リードフレーム、2:半導体チツプ、3:
ITVカメラ、4:映像信号処理回路、5:メモ
リ、6:比較回路、7:制御装置。
The figure is a block diagram of an embodiment according to the invention. 1: Lead frame, 2: Semiconductor chip, 3:
ITV camera, 4: video signal processing circuit, 5: memory, 6: comparison circuit, 7: control device.
Claims (1)
の電極にキヤピラリイからワイヤを供給してワイ
ヤボンデイングを行う方式において、撮像装置に
よりボンデイング作業位置に送られたリードフレ
ーム上の半導体チツプ映像信号を取り込んで該チ
ツプ映像信号を記憶させるとともに、該チツプ映
像信号により電極位置を認識し、該認識内容に基
いてキヤピラリイを位置決めしてワイヤの一端を
電極位置に第1ボンデイングし、キヤピラリイと
リードフレームを相対的に変位させて上記ワイヤ
の他端を第2ボンデイングするべき位置にキヤピ
ラリイを位置決めし、該キヤピラリイ位置決め期
間に同時に上記ボンデイング作業位置の半導体チ
ツプ映像信号を上記撮像装置により再度取り込
み、該チツプ映像信号と上記第1ボンデイング前
に予め取り込み記憶されたチツプ映像信号とを比
較して、第1ボンデイング後のチツプの剥れ又は
チツプ或いは電極の一部剥れを検出し、該剥れを
検出したときは上記第2のボンデイングを停止す
ることを特徴とする半導体用自動ワイヤボンデイ
ング方式。1 In a method in which wire bonding is performed by supplying wires from a capillary to electrodes on a semiconductor chip mounted on a lead frame, the image signal of the semiconductor chip on the lead frame sent to the bonding work position by an imaging device is captured and the image signal is transferred to the chip. The video signal is stored, the electrode position is recognized by the chip video signal, the capillary is positioned based on the recognized content, one end of the wire is first bonded to the electrode position, and the capillary and the lead frame are relatively displaced. Then, the capillary is positioned at a position where the other end of the wire is to be subjected to second bonding, and at the same time during the capillary positioning period, the semiconductor chip video signal at the bonding work position is captured again by the imaging device, and the chip video signal and the semiconductor chip video signal are By comparing the chip video signal captured and stored in advance before the first bonding, peeling of the chip after the first bonding or partial peeling of the chip or electrode is detected, and when such peeling is detected, the above-mentioned An automatic wire bonding method for semiconductors characterized by stopping step 2 of bonding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2747979A JPS55120144A (en) | 1979-03-08 | 1979-03-08 | Automatic wire bonding system for semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2747979A JPS55120144A (en) | 1979-03-08 | 1979-03-08 | Automatic wire bonding system for semiconductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55120144A JPS55120144A (en) | 1980-09-16 |
JPS6150381B2 true JPS6150381B2 (en) | 1986-11-04 |
Family
ID=12222251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2747979A Granted JPS55120144A (en) | 1979-03-08 | 1979-03-08 | Automatic wire bonding system for semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55120144A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3298795B2 (en) * | 1996-07-16 | 2002-07-08 | 株式会社新川 | How to set lead frame transport data |
DE502004005212D1 (en) * | 2004-08-11 | 2007-11-22 | F & K Delvotec Bondtech Gmbh | Wire bonder with a camera, an image processing device, storage means and comparator means and method of operating such |
-
1979
- 1979-03-08 JP JP2747979A patent/JPS55120144A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55120144A (en) | 1980-09-16 |
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