JPS6150339A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6150339A
JPS6150339A JP59171953A JP17195384A JPS6150339A JP S6150339 A JPS6150339 A JP S6150339A JP 59171953 A JP59171953 A JP 59171953A JP 17195384 A JP17195384 A JP 17195384A JP S6150339 A JPS6150339 A JP S6150339A
Authority
JP
Japan
Prior art keywords
tool
semiconductor element
electrodes
metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59171953A
Other languages
Japanese (ja)
Other versions
JPH0357617B2 (en
Inventor
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59171953A priority Critical patent/JPS6150339A/en
Publication of JPS6150339A publication Critical patent/JPS6150339A/en
Publication of JPH0357617B2 publication Critical patent/JPH0357617B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]

Abstract

PURPOSE:To perform junction process at low cost reducing the time required by a method wherein metallic bumps are provided on a substrate with their positions aligned with those of semiconductor element electrodes to be transferred to the bottom of a tool while the metallic bumps are further aligned with the semiconductor element electrodes. CONSTITUTION:(a): A tool 3 with bottom size similar to that of a semiconductor element chip aligned with metallic bumps 2 is lowered. (b): Firstly the tool 3 is brought into contact with the metallic bumps 2 on a substrate 1 to be pressurized and heated so that the bumps 2 may be transferred and junctioned to the bottom of tool 3. (c): Secondly the metallic bumps 2 transferred and junctioned to the tool 3 preliminarily aligned with electrodes 6 of a semiconductor element 5 are pressurized and heated 7. (d): Thirdly the tool 3 is lifted up leaving the metallic bumps 2 junctioned to the electrodes 6 of substrate element 5. Through these procedures, any conventional complicated processes such as barrier metal forming and etching, etc. may be eliminated.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子もしくは半導体素子を搭載するため
の基板に金属突起を形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming metal protrusions on a semiconductor element or a substrate for mounting a semiconductor element.

従来例の構成とその問題点 近年、半導体素子を多数個用いるデバイス、機器の開発
が促進されてきている。例えば、メモリーカード、液晶
やＥＬディスプレイパイ・ル等があり、これらは、いず
れも多数個のＩＣ，ＬＳＩを一定の面積を有する基板に
、高密度にしかも薄型に搭載しなければならない。ＩＣ
，ＬＳＩの高密度の実装手段として、フィルムキャリヤ
方式やフリップテップ方式が公知であるが、次の様な問
題がある。2. Description of the Related Art Conventional configurations and their problems In recent years, the development of devices and equipment that use a large number of semiconductor elements has been accelerated. For example, there are memory cards, liquid crystal displays, EL display piles, etc., all of which require a large number of ICs and LSIs to be mounted thinly and at high density on a substrate having a certain area. IC
, Film carrier methods and flip-step methods are known as high-density mounting means for LSIs, but they have the following problems.

いずれの方式も半導体素子の電極上に外部端子と接続す
るための金属突起を形成しなければならない。金属突起
を形成するために、半導体素子表面にバリヤメタルと呼
ばれるＣｒ　−Ｃｕ　、　Ｔ　ｉ　−Ｐｄ等の多層金属
膜を被着し、次いで、前記半導体素子の電極に相当する
領域を開孔した°感光性樹脂パターンを形成する。前記
多層金属膜を一方の電極とし、前記開孔部にＡｕ　、　
Ｃｕ　、　Ａｇ　、半田等のメッキ処理をし、１０〜３
０μｍの高さの金属突起を形成し、不要となった感光性
樹脂パターンおよび多層金属膜の一部を除去する。この
様に半導体素子の電極上に金属突起を形成するのに、多
数の工程を必要とし、この工程の途中において前記半導
体素子に損傷を与え、歩留りを低下さす原因となってい
た。このために著しるしく製造コストが高くなるばかり
か、信頼性おも低下さすものであった。In either method, metal protrusions must be formed on the electrodes of the semiconductor element for connection to external terminals. In order to form metal protrusions, a multilayer metal film called a barrier metal such as Cr-Cu, Ti-Pd, etc. is deposited on the surface of the semiconductor element, and then holes are opened in areas corresponding to the electrodes of the semiconductor element. form a synthetic resin pattern. The multilayer metal film is used as one electrode, and Au,
Plating with Cu, Ag, solder, etc.,
Metal protrusions with a height of 0 μm are formed, and unnecessary photosensitive resin patterns and part of the multilayer metal film are removed. In this way, forming metal protrusions on the electrodes of a semiconductor element requires a large number of steps, which causes damage to the semiconductor element during these steps, resulting in a decrease in yield. This not only significantly increases manufacturing costs but also reduces reliability.

発明の目的 本発明はこのような従来の問題に鑑み、接続時工程が著
しるしく少なく、安価な接続方法を提供することを目的
とする。OBJECTS OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide an inexpensive connection method with significantly fewer steps during connection.

発明の構成 本発明は、基板上に半導体素子の電極に対応した位置に
金属突起を設け、この金属突起をツールに転写し、次い
で例えば半導体素子の電極と前記１　　　　　　　１鼾
詠″ｆｆ１ｌれ・加１°加１＠ｔ６ｃ、！：によって、
前記金属突起を半導体素子の電極に接合する構成である
。Structure of the Invention The present invention provides metal protrusions on a substrate at positions corresponding to the electrodes of a semiconductor element, transfers the metal protrusions to a tool, and then, for example, attaches the metal protrusions to the electrodes of the semiconductor element and the above-mentioned 1. 1°+1@t6c,!: by,
The structure is such that the metal protrusion is bonded to an electrode of a semiconductor element.

実施例の説明 第１図で第１の実施例を説明する。基板１はセラミック
、ガラス等の絶縁体上にメッキ用電極となる金属膜が形
成され、更にその上に絶縁膜が形成され半導体素子の電
極と対応した位置に開孔部を有し、前記開孔部に金属突
起２が形成される。DESCRIPTION OF THE EMBODIMENTS A first embodiment will be explained with reference to FIG. The substrate 1 has a metal film to serve as a plating electrode formed on an insulator such as ceramic or glass, and an insulating film formed thereon, and has an opening at a position corresponding to the electrode of the semiconductor element. A metal protrusion 2 is formed in the hole.

金属突起２け例えばＡｕで構成され、電解メッキ法で前
記開孔部上に形成される。ついで、少なくとも半導体素
子のチップ寸法と同一寸法の底面をしたツール３と前記
金属突起２とを位置合せし、ツール３を下降４せしめる
（第１図ａ）。The two metal protrusions are made of, for example, Au and are formed on the openings by electrolytic plating. Next, the metal protrusion 2 is aligned with the tool 3 whose bottom surface has at least the same size as the chip size of the semiconductor element, and the tool 3 is lowered 4 (FIG. 1a).

ツール３を基板１上の金属突起２に接触させ加圧・加熱
せしむれば基板１上の金属突起２けツール３の底面に転
写・接合される（第１図ｂ）。基板の構成については第
３図で詳細にのべるが、金属突起を形成する開孔部内の
下地の金属膜はメッキ処理が容易で、かつ容易に剥離で
きる材料で構成される。またツール３は、その底面が多
少の凹凸を有し、金属突起と接し、加圧加熱されること
により、前記凹凸に金属突起が微少に喰い込み、金属突
起がツール側に転写する構成であっても良いし、ツール
底面に前記金属突起とルミ的合金を形成しやすい材料が
設けられており、金属突起と接した時に、少量の合金を
形成することＫよってツール側に金属突起が転写される
構成であっても良い。When the tool 3 is brought into contact with the metal projections 2 on the substrate 1 and pressurized and heated, the metal projections 2 on the substrate 1 are transferred and bonded to the bottom surface of the tool 3 (FIG. 1b). The structure of the substrate will be described in detail in FIG. 3, but the underlying metal film in the opening where the metal protrusion is formed is made of a material that can be easily plated and easily peeled off. Moreover, the tool 3 has a structure in which the bottom surface has some irregularities, and when it comes into contact with metal protrusions and is heated under pressure, the metal protrusions bite into the irregularities slightly, and the metal protrusions are transferred to the tool side. Alternatively, the bottom surface of the tool is provided with a material that easily forms a luminous alloy with the metal protrusion, and when it comes into contact with the metal protrusion, a small amount of alloy is formed, thereby transferring the metal protrusion to the tool side. It may also be a configuration.

次に、ツール３に転写・接合された金属突起２は半導体
素子５の電極６と位置合せし、ノール３で加圧・加熱了
しく第１図Ｃ）、ツール３を上昇８させれば、金属突起
２は半導体素子５の電極６上に接合される（第１図ｄ）
。ツール３の加圧・加熱条件（ｄ、金属突起２がＡｕで
、半導体素子６の電極６がアルミニウム電極で構成され
るならば、半導体素子５を１００℃〜３００’Ｃに加熱
した状態ならば、ツールの温度は３５０℃〜５ｏｏ℃、
加圧力は金属突起１個蟲り３０７〜１００ｙで接合でき
る。Next, the metal projections 2 transferred and bonded to the tool 3 are aligned with the electrodes 6 of the semiconductor element 5, and after applying pressure and heating with the knoll 3 (FIG. 1C), the tool 3 is raised 8. The metal protrusion 2 is bonded onto the electrode 6 of the semiconductor element 5 (FIG. 1d)
. Pressure/heating conditions of the tool 3 (d) If the metal protrusion 2 is made of Au and the electrode 6 of the semiconductor element 6 is composed of an aluminum electrode, if the semiconductor element 5 is heated to 100°C to 300'C. , the temperature of the tool is 350℃~5oo℃,
The pressing force can be 307 to 100 y for one metal protrusion.

次に他の実施例を第２図で説明する。基板上の金属突起
２をツール３に転写・接合した後、回路基板１ｏの配線
パターン１１と位置合せし、ツール３を下降せしめる（
第２図ａ）。ツールを下降し、加圧・加熱すればツール
３の金属突起２は回路基板１Ｑの配線パターン１１側に
接合される（第２図ｂ）。これにより配線パターン上に
金属突起が形成される。前記回路基板１ｏはエボキン。Next, another embodiment will be explained with reference to FIG. After transferring and bonding the metal protrusion 2 on the board to the tool 3, it is aligned with the wiring pattern 11 of the circuit board 1o, and the tool 3 is lowered (
Figure 2 a). When the tool is lowered and pressurized and heated, the metal protrusion 2 of the tool 3 is joined to the wiring pattern 11 side of the circuit board 1Q (FIG. 2b). As a result, metal protrusions are formed on the wiring pattern. The circuit board 1o is Evokin.

ガラス、セラミックあるいは金属を母体にし表面に絶縁
体を形成した材料であり、配線バターハ１は、Ａｕ又は
Ｃｕ、Ａｇで形成され、Ｃｕの場合にはその表面にＳｎ
　　、半田、Ａｕ等の膜が形成され、金属突起２と容易
に合金を形成しやすい材料を用いるものである。次にノ
ール１３で半導体素子５を保持し、半導体素子５の電極
６と配線バター７１１上の金属突起２とを位置合せ（第
２図Ｃ）Ｌ、ツール１３を下降１２せしめ、加圧・加熱
（第１の実施例で説明した条件と同じ）し、ツール１３
を上昇１４すれば第２図ｄの如く半導体素子６の電極６
と配線パターン１１上の金属突起２とが接合されるもの
である。It is a material made of glass, ceramic, or metal as a matrix and an insulator is formed on the surface.
A film such as , solder, or Au is formed, and a material that easily forms an alloy with the metal protrusion 2 is used. Next, hold the semiconductor element 5 with the knoll 13, align the electrode 6 of the semiconductor element 5 and the metal protrusion 2 on the wiring butter 711 (FIG. 2C) L, lower the tool 13 12, and apply pressure and heat. (same conditions as described in the first example) and tool 13
When the electrode 6 of the semiconductor element 6 is raised 14, as shown in FIG.
and the metal protrusion 2 on the wiring pattern 11 are joined.

以上のべた如く本発明は金属突起を別の基板に形成し、
これをツールに転写、次いで半導体素子あるいは配線パ
ターンに加圧・加熱により接合せしめるものでちる。し
たがって、従来の如くバリヤメタルの形成やエツチング
等め複雑な工程を必要としない。As described above, the present invention forms metal protrusions on another substrate,
This is transferred to a tool and then bonded to a semiconductor element or wiring pattern by applying pressure and heating. Therefore, there is no need for complicated processes such as forming barrier metal and etching as in the prior art.

次に本発明の金属突起を形成するための基板の構成例に
ついて第３図で説明する。ガラス、セラミック等の絶縁
体２０上にｉｔｏ、Ｐｔ、Ｐｄ等のメッキの形成が良好
でかつ耐着力の弱い導電性材料２１を全面に設け、この
上に半導体素子の電極と対応した位置に開孔２３を有す
る５１０２，５１３Ｎ４゜Ａｔ２０３等の絶縁膜２２を
形成する。導電性材料２１を一方の電極として電解メッ
キ処理すれは開孔部２３に金属突起２４が形成される。Next, an example of the structure of a substrate for forming metal protrusions of the present invention will be explained with reference to FIG. A conductive material 21 with good plating such as ITO, Pt, or Pd and having weak adhesion strength is provided on the entire surface of an insulator 20 such as glass or ceramic, and an opening is formed on the insulator 20 at a position corresponding to the electrode of the semiconductor element. An insulating film 22 of 5102, 513N4°At203 or the like having holes 23 is formed. After electroplating using the conductive material 21 as one electrode, a metal protrusion 24 is formed in the opening 23 .

金属突起２４がツールに転写・接合され、基板２０上に
金属突起２４が存在しなくなれば、再度メッキ処理し、
繰返し前記基板を用いるものである０ 発明の効果 １　　　　　　　（１）　　半導体素子の電極や配線パ
ターン上に金属突起を形成するのに、従来必要としてい
たバリャメ、　タルの形成、フォトリングラフィ、エツ
チング等の工程がまったく不要となり、製造コストが著
しるしく安価となりまた半導体素子や配線パターンに処
理する必要がないので歩留りの低下や信頼性を低下さす
事がない。Once the metal protrusions 24 are transferred and bonded to the tool and no longer exist on the substrate 20, plating is performed again.
0 Effects of the Invention 1 (1) In order to form metal protrusions on the electrodes and wiring patterns of semiconductor elements, it is possible to eliminate the conventional processes such as barrier, barrel formation, photolithography, etching, etc. No process is required, the manufacturing cost is significantly reduced, and there is no need to process semiconductor elements or wiring patterns, so there is no reduction in yield or reliability.

（２）基板上に形成した金属突起を−たんツールに転写
接合するために、金属突起間の位置寸法が変動すること
なく正確に設定され、半導体素子の電極や配線パターン
忙接合できるため、不完全な信頼性の低い接合が発生し
ないばかりか、基板から金属突起を転写・接合する時お
よび半導体素子の電極や配線パターンに接合する時の位
置合せか、ツールの外寸によって設定できるので、位置
合せが著じるしく容易である。すなわちツールの底面の
外寸を半導体素子の外寸と同じくすれば、お互いの外寸
のみを重なる如く位置合せすれば良く、微細な半導体素
子の電極と金属突起の精度の高い位置合せを必要としな
い。この事は、同様に、金属突起を形成する基板、配線
パターン上に前記ツールの外寸と同じになる位置合せマ
ークを形成しておけば良いものである。(2) Because the metal protrusions formed on the substrate are simply transferred and bonded to the tool, the positional dimensions between the metal protrusions can be set accurately without fluctuations, and the electrodes and wiring patterns of semiconductor elements can be bonded without any hassle. Not only will a completely unreliable bond not occur, but the positioning can be set by the external dimensions of the tool when transferring and bonding metal protrusions from the substrate or when bonding to the electrodes and wiring patterns of semiconductor elements. It is extremely easy to match. In other words, if the outer dimensions of the bottom of the tool are made the same as the outer dimensions of the semiconductor element, it is only necessary to align the two outer dimensions so that they overlap, which requires highly accurate alignment of the minute electrodes of the semiconductor element and the metal protrusions. do not. This can be achieved by forming alignment marks having the same external dimensions as the tool on the substrate and wiring pattern on which the metal protrusions are to be formed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａ　−ｄは本発明の第１の実施例を示す工程断面
図、第２図ａ−ｄは本発明の他の実施例を示す工程断面
図、第３図は金属突起を形成する基板の断面図である。 １・・・・・・基板、２・・・・・金属突起、３・・・
・・ツール、５・・・・・・半導体素子、６・・・・・
電極、１０・・・・・・回路基板、１１・・・・・・配
線パターン。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名−の ″′　　　味Figures 1 a - d are process cross-sectional views showing a first embodiment of the present invention, Figures 2 a - d are process cross-sectional views showing other embodiments of the present invention, and Figure 3 is a process cross-sectional view showing the process of forming a metal protrusion. FIG. 3 is a cross-sectional view of the substrate. 1...Substrate, 2...Metal protrusion, 3...
...Tool, 5...Semiconductor element, 6...
Electrode, 10...Circuit board, 11...Wiring pattern. Name of agent: Patent attorney Toshio Nakao and 1 other person

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子の電極と対応した位置に金属突起物を
形成した基板の前記金属突起物にツールを接触させ加圧
・加熱し、前記基板上の金属突起物を剥離しツールに転
写・接合する工程前記半導体素子の電極と前記ツール上
の金属突起物とを位置合せ、接合する工程により前記基
板上の金属突起物を半導体素子の電極上に転写・接合す
る事を特徴とする半導体装置の製造方法。(1) A tool is brought into contact with the metal protrusions of a substrate on which metal protrusions are formed at positions corresponding to the electrodes of the semiconductor element, pressure is applied and heated, and the metal protrusions on the substrate are peeled off and transferred and bonded to the tool. A semiconductor device characterized in that the metal protrusions on the substrate are transferred and bonded onto the electrodes of the semiconductor element by the step of aligning and bonding the electrodes of the semiconductor element and the metal protrusions on the tool. Production method. （２）ツールに基板上の金属突起物を転写・接合した後
、配線基板上の電極と前記ツール上の金属突起物とを位
置合せ、接合し、前記基板上の金属突起物を配線基板の
電極上に転写・接合する事を特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。(2) After transferring and bonding the metal protrusions on the board to the tool, align and bond the electrodes on the wiring board and the metal protrusions on the tool, and transfer the metal protrusions on the board to the wiring board. A method for manufacturing a semiconductor device according to claim 1, characterized in that the semiconductor device is transferred and bonded onto an electrode.
JP59171953A 1984-08-18 1984-08-18 Manufacture of semiconductor device Granted JPS6150339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59171953A JPS6150339A (en) 1984-08-18 1984-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59171953A JPS6150339A (en) 1984-08-18 1984-08-18 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6150339A true JPS6150339A (en) 1986-03-12
JPH0357617B2 JPH0357617B2 (en) 1991-09-02

Family

ID=15932842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59171953A Granted JPS6150339A (en) 1984-08-18 1984-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6150339A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7312785B2 (en) 2001-10-22 2007-12-25 Apple Inc. Method and apparatus for accelerated scrolling
US8059099B2 (en) 2006-06-02 2011-11-15 Apple Inc. Techniques for interactive input to portable electronic devices
US20070152983A1 (en) 2005-12-30 2007-07-05 Apple Computer, Inc. Touch pad with symbols based on mode
US9360967B2 (en) 2006-07-06 2016-06-07 Apple Inc. Mutual capacitance touch sensing device
US8743060B2 (en) 2006-07-06 2014-06-03 Apple Inc. Mutual capacitance touch sensing device
US8416198B2 (en) 2007-12-03 2013-04-09 Apple Inc. Multi-dimensional scroll wheel
US9454256B2 (en) 2008-03-14 2016-09-27 Apple Inc. Sensor configurations of an input device that are switchable based on mode
US9354751B2 (en) 2009-05-15 2016-05-31 Apple Inc. Input device with optimized capacitive sensing
US8872771B2 (en) 2009-07-07 2014-10-28 Apple Inc. Touch sensing device having conductive nodes

Also Published As

Publication number Publication date
JPH0357617B2 (en) 1991-09-02

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