JPS6150333A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS6150333A JPS6150333A JP17226984A JP17226984A JPS6150333A JP S6150333 A JPS6150333 A JP S6150333A JP 17226984 A JP17226984 A JP 17226984A JP 17226984 A JP17226984 A JP 17226984A JP S6150333 A JPS6150333 A JP S6150333A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- integrated circuit
- semiconductor integrated
- feasible
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路の製造方法、特に配線技術に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit, and in particular to wiring technology.
従来例の構成とその問題点
近年、Ｇａ Ａｓ集積回路装置は超高速素子として急速
に開発が進められている。その中で配線技術はその成否
を握る要素技術の一つである。Conventional Structure and its Problems In recent years, GaAs integrated circuit devices have been rapidly developed as ultra-high-speed devices. Wiring technology is one of the elemental technologies that determines success or failure.
以下図面を参照しながら、従来の配線について説明する
。第１図は従来の配線技術によって配線゛されたＱａ
ＡＳ素子の断面を示す。第１図において、１は半絶縁性
Ｑａ Ａｓ基板、２は活性層、３はｉ−ミック電極、４
はＴｉＦｌｌ、５はＡＩＪ！９．６はＳｉＯ２股である
。Conventional wiring will be described below with reference to the drawings. Figure 1 shows Qa wired using conventional wiring technology.
A cross section of an AS element is shown. In FIG. 1, 1 is a semi-insulating Qa As substrate, 2 is an active layer, 3 is an i-mic electrode, and 4 is a semi-insulating Qa As substrate.
is TiFll, 5 is AIJ! 9.6 is a SiO 2-piece.
以上のように構成された配線について説明をする。まず
半絶縁性Ｑａ Ａｓ基板１に活性層２を形成した後、Ａ
−ミンク接合形成のため△ｕｓｅ／ＡＬ＋等のオーミッ
ク金属と蒸着し、リフ］・オフ法で電極３を形成する。The wiring configured as above will be explained. First, after forming an active layer 2 on a semi-insulating QaAs substrate 1,
- To form a mink junction, an ohmic metal such as Δuse/AL+ is vapor-deposited, and the electrode 3 is formed by a riff]-off method.
アロイ処ＦＴｌ後、局間絶縁膜としてＳｉＯ２膜６を成
長し、その模にコンタクト窓を間１プてＴｉ膜４および
Ａ ｕ Ｆｆ！ ５を蒸右する。After the alloy treatment FTl, a SiO2 film 6 is grown as an inter-office insulating film, and a contact window is formed in the pattern to form a Ti film 4 and A u Ff! Steam 5.
この後、ヨードエツチング液でＡｕ膜５をエツチングし
、過酸化水素系エツチング液でＴｉ１ｌｆ！４をエツチ
ングして配線とする。After that, the Au film 5 is etched with an iodine etching solution, and the Ti1lf! is etched with a hydrogen peroxide based etching solution. 4 is etched to form wiring.
しかしながら、上記のような構成では高価なＡｌｌを多
量に必要とするのみならず、Ａｌｌのドライ〕−ツチン
グ速度・は極めて遅いため、先に述べたウェットエツチ
ングを用いねばならない。ウェットエツチングは微細加
工が困ガであり、特にＴ；膜の、エツチング速度は極め
て速いための制御がガしく、集積回路用の配線としては
不適当であった。However, the above-mentioned structure not only requires a large amount of expensive Al, but also the dry etching speed of All is extremely slow, so the wet etching described above must be used. Wet etching is difficult to microfabricate, and the etching rate of the T film in particular is extremely fast, making it difficult to control, making it unsuitable for wiring for integrated circuits.
発明の目的
本発明は上記欠点に鑑み、精度の高いドライエツチング
が適用でき、また、安価に配線を得ることのできる半導
体集積回路の製造方法を提供づるものである。OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a semiconductor integrated circuit in which highly accurate dry etching can be applied and wiring can be obtained at low cost.
発明の構成
上記目的を達成するために、本発明の半導体集積回路の
製造方法は、Ａｕと、Ｔｉ とＡ１の３層構造で配線で
きるように構成したもので、これにより、Ｔｉ１ｌＪｌ
がＡｕ膜のバリアとして働き、ＡｕとＡ１の共晶化が防
止され、Ａ１による配線が可能となるものである。Structure of the Invention In order to achieve the above object, the method for manufacturing a semiconductor integrated circuit of the present invention is configured so that wiring can be performed in a three-layer structure of Au, Ti, and A1.
serves as a barrier for the Au film, preventing eutectic formation of Au and A1, and enabling wiring using A1.
実施例の説明
以下本発明の一実施例について、図面を参照しながら説
明する。第２図は本発明の一実施例における半導体集積
回路の製造方法によって配線したＧａ Ａｓ素子の断面
を示す。第２図において、７はオーミック金属のＡｕ膜
、８はバリアとしてのｌ Ｔｉ膜、９はＡ
Ｉ配線層である。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a cross section of a GaAs element wired by a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention. In Figure 2, 7 is an ohmic metal Au film, 8 is a Ti film as a barrier, and 9 is A
This is the I wiring layer.
このように構成された配線について、以下その製造工程
を説明をする。まず半絶縁性Ｇａ Ａｓ ％板１に３ｉ
をイオン注入して活性層２を形成する。The manufacturing process for the wiring configured in this way will be explained below. First, semi-insulating GaAs % plate 1 is 3i
The active layer 2 is formed by ion implantation.
活性化後Ｓｉ ０２．６を５０００Ａ成長し、Ａ−ミン
ク電極部分に窓を開ける。ここにＴｉ ４／Ａｕ ５を
１０００人／ １５００Ａ Ｍ子ビーム蒸着してリフト
オフする。Ｈ２ガス中５００℃でアロイしてオーミック
接合を形成後、逆スパツタでＴｉ表面の酸化膜を除去し
、直ちにＡ１を５０００Ａ蒸着する。次に、レジストマ
スクをかけ、Ｃ，ＣＩ４ガスでドライエツチングをして
配線層９を形成する。After activation, Si 02.6 is grown at 5000A, and a window is opened in the A-mink electrode portion. Ti 4/Au 5 was then evaporated with a beam of 1,000 people/1,500 amps and lifted off. After forming an ohmic junction by alloying at 500° C. in H2 gas, the oxide film on the Ti surface is removed by reverse sputtering, and immediately A1 is vapor-deposited at 5000A. Next, a resist mask is applied and dry etching is performed using C and CI4 gases to form a wiring layer 9.
このような本実施例によれば、ＴｉがＡｕＡ＋の共晶化
を防ぐバリアとして働く。したがってオーミック電極部
分がＡ１劣化する問題が解消され、ＡＩを配線層として
用いることができる。According to this embodiment, Ti acts as a barrier to prevent AuA+ from becoming eutectic. Therefore, the problem of A1 deterioration in the ohmic electrode portion is solved, and AI can be used as a wiring layer.
発明の効果
以上のように本発明は、配線層の一部をＡｕとＴｉ と
Ａ１の３ｍ構造で配線するようにしたので、オーミック
特性は従来と変らない良好な特性を有し、配線部分には
安価でドライエツチング可能なＡＩを使用でき、その実
用的効果は大なるものがある。Effects of the Invention As described above, in the present invention, a part of the wiring layer is wired in a 3m structure of Au, Ti, and A1, so the ohmic characteristics are as good as the conventional ones, and the wiring part is It is possible to use AI, which is inexpensive and can be dry-etched, and its practical effects are great.
第１図は従来の配線によるＧａ Ａｓ素子の断面図、第
２図は本発明の一実施例における配線によるＱａ Ａｓ
素子の断面図である。
１・・・半絶縁性Ｇａ Ａｓ基板、２・・・活性層、６
・・・５ｉ０２膜、７・ＡＬＩＩＩＩＩ、ｅ、 ・Ｔ
ｉ膜、９ ・Ａ Ｉ配線層
代理人 森 本 義 弘
第ｆ図
第２図FIG. 1 is a cross-sectional view of a GaAs element using conventional wiring, and FIG. 2 is a cross-sectional view of a GaAs element using wiring according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the element. DESCRIPTION OF SYMBOLS 1...Semi-insulating GaAs substrate, 2...Active layer, 6
...5i02 membrane, 7・ALIII, e, ・T
I film, 9 ・A I wiring layer agent Yoshihiro Morimoto Figure f Figure 2
Claims (1)
ｕ膜、Ｔｉ膜を形成した後、Ａｌ膜を形成し、Ａｌ膜に
より配線する半導体集積回路の製造方法。1. When forming wiring electrodes, A is applied to the surface of the semiconductor substrate.
A method for manufacturing a semiconductor integrated circuit, in which a U film and a Ti film are formed, an Al film is formed, and wiring is formed using the Al film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17226984A JPS6150333A (en) | 1984-08-18 | 1984-08-18 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17226984A JPS6150333A (en) | 1984-08-18 | 1984-08-18 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6150333A true JPS6150333A (en) | 1986-03-12 |
Family
ID=15938769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17226984A Pending JPS6150333A (en) | 1984-08-18 | 1984-08-18 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6150333A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007267094A (en) * | 2006-03-29 | 2007-10-11 | Seiko Npc Corp | Receiver ic |
| JP2016143723A (en) * | 2015-01-30 | 2016-08-08 | 住友電工デバイス・イノベーション株式会社 | Method for manufacturing semiconductor device |
-
1984
- 1984-08-18 JP JP17226984A patent/JPS6150333A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007267094A (en) * | 2006-03-29 | 2007-10-11 | Seiko Npc Corp | Receiver ic |
| JP2016143723A (en) * | 2015-01-30 | 2016-08-08 | 住友電工デバイス・イノベーション株式会社 | Method for manufacturing semiconductor device |
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