JPS63245961A - Manufacture of t-shaped gate - Google Patents
Manufacture of t-shaped gateInfo
- Publication number
- JPS63245961A JPS63245961A JP8151387A JP8151387A JPS63245961A JP S63245961 A JPS63245961 A JP S63245961A JP 8151387 A JP8151387 A JP 8151387A JP 8151387 A JP8151387 A JP 8151387A JP S63245961 A JPS63245961 A JP S63245961A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- overlay
- insulating layer
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果トランジスタに関し、特KT型ゲート
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor, and particularly to a method for manufacturing a KT type gate.
電界効果素子の高周波化においてゲート長の短縮化に必
須であるが逆にこの事によりゲート断面積が小さくなシ
ゲート抵抗が大きくなる。そζでゲート断面構造を第2
図に示すようにT型としゲート抵抗を減らす事が従来性
なわれている。この種の形状の電極は第3図に示すいわ
ゆるオーバレイ構造におけるゲートと同形状であるが、
このままであるとオーバレイ下部の浮遊容量大きく、こ
れを避ける為にはオーバレイ下部の絶縁層を除去する必
要がある。This is essential for shortening the gate length when increasing the frequency of field effect devices, but conversely, this increases the siggate resistance with a small gate cross-sectional area. Then, the gate cross-sectional structure is determined as the second
As shown in the figure, the conventional practice is to use a T-shape to reduce gate resistance. This type of shaped electrode has the same shape as the gate in the so-called overlay structure shown in FIG.
If left as is, the stray capacitance below the overlay will be large, and to avoid this, it is necessary to remove the insulating layer below the overlay.
しかしながらこの絶縁層部を除去する際、ゲートを形成
する金属層も同時に浸食される恐れがるる。例えば通常
、上記絶縁層として8i01が用いられる場合が多く、
またゲートを購成する金属層には通常、シ言ットキ金属
の上にゲート抵抗を小さくする為にAu等の低抵抗金属
を被着するが、さらにこれら金属の密着性を良くする為
にTi等の金属が中間に介在した構成となる。そこで前
述のSin!を弗酸によシエッチングした場合、同時に
Ti も側面よシエッチングされる。この欠点を補う方
法として例えばフォトレジスト等によってゲートを保護
した後エツチングする事が考えられる。しかしゲート寸
法が短い場合、精度よくゲートをカバーする事は困難と
なる。つまシ少しの目づれによりゲートが露出し、結局
当方法にては前述の危険性は回避できない。However, when this insulating layer portion is removed, there is a fear that the metal layer forming the gate will also be eroded at the same time. For example, 8i01 is usually used as the insulating layer,
Furthermore, in order to reduce the gate resistance, a low resistance metal such as Au is usually coated on top of the metal layer for the gate, but in order to further improve the adhesion of these metals, Ti is coated on top of the metal layer. It has a structure in which metals such as are interposed in the middle. So the aforementioned Sin! When Ti is etched with hydrofluoric acid, the sides of Ti are also etched at the same time. A conceivable way to compensate for this drawback is to protect the gate with a photoresist or the like and then perform etching. However, when the gate size is short, it is difficult to cover the gate with accuracy. A slight misalignment of the tab will expose the gate, and in the end, this method cannot avoid the above-mentioned danger.
本発明はこれらの欠点を補なりたものであシ、オーバレ
イゲート形成後、オーバレイ下部の絶縁膜とは異なる絶
縁膜によりゲート側面を保護し然る後オーバレイ下部の
絶縁膜のみを浸食するエツチング液にて除去する事を特
徴とする。The present invention compensates for these drawbacks by protecting the sides of the gate with an insulating film different from the insulating film below the overlay after forming the overlay gate, and then using an etching solution that erodes only the insulating film below the overlay. It is characterized by being removed by.
更に詳細に述べると、まず、平坦なウニノー−に部分的
に金属層等の段差がある場合、この上にCVD法等によ
り成長されたSiO!、5isN番等の絶縁膜を上記金
属層と選択性のあるガスにて異方的にドライエツチング
し、金属層側壁にのみ上記絶縁膜を残す技術は、側壁加
工技術として周知である。従ってオーバレイゲート形成
後、オーバレイ下部の絶縁膜とは異なる絶縁膜を成長し
、上記側壁加工技術を用いる事によシゲート側面はオー
バレイ下部の絶縁膜とは異なる絶縁膜によシ保護される
。然る後、上記2種の絶縁膜に対し選択性のあるエツチ
ング液にてオーバレイ下部の絶縁膜をエツチングする事
によシ目的を達成できる。To explain in more detail, first, if there is a partial step such as a metal layer on a flat surface, SiO! , 5isN, or the like is anisotropically dry-etched using a gas selective to the metal layer, and the technique of leaving the insulating film only on the sidewalls of the metal layer is well known as a sidewall processing technique. Therefore, after forming the overlay gate, by growing an insulating film different from the insulating film below the overlay and using the above-mentioned sidewall processing technique, the side surfaces of the gate are protected by the insulating film different from the insulating film below the overlay. After that, the purpose can be achieved by etching the insulating film below the overlay using an etching solution that is selective to the above two types of insulating films.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(C)は本発明によるT型ゲート製法の
一実施例である。まず第1図(a)はオーバレイゲート
形成後の断面図であシ絶縁膜はSin、、またゲート金
属構成はWS i −T i −P t−Auである。FIGS. 1(a) to 1(C) show an embodiment of the T-type gate manufacturing method according to the present invention. First, FIG. 1(a) is a cross-sectional view after the overlay gate is formed.The insulating film is made of Sin, and the gate metal composition is WSi-Ti-Pt-Au.
PtはAu拡散防止用であシ、膜厚は例えば5iOt=
法によfi2000A成長する。次に例えばCF、ガス
を用いたRIEによ)上記Si3N4を上記膜厚値程度
ドライエツチングし第1図(b)に示すようにゲート側
壁にのみsi、N、を残す。次に例えば弗酸:弗化アン
モニウム=に6の液にてオーバレイ下部の5i02をエ
ツチングする事によシ第1図(c)K示すT型ゲートを
得る。Pt is for preventing Au diffusion, and the film thickness is, for example, 5iOt=
Grow fi2000A by law. Next, the Si3N4 is dry etched to the above film thickness (by RIE using CF gas, for example), leaving Si and N only on the gate sidewalls as shown in FIG. 1(b). Next, the T-shaped gate shown in FIG. 1(c)K is obtained by etching the lower part of the overlay 5i02 using, for example, a hydrofluoric acid:ammonium fluoride solution (6).
以上説明したように本発明によれば、T型ゲート構造を
有する電界効果トランジスタにおいて、その浮遊容量の
ため特性を阻害するオーバレイ下部の絶縁膜を、ゲート
側壁を左記オーバレイ下部の絶縁膜とは異なる絶縁膜に
よシ保役する事によシ、ゲート金属を浸食することなく
除去する事ができる。As explained above, according to the present invention, in a field effect transistor having a T-type gate structure, the insulating film at the bottom of the overlay, which inhibits characteristics due to its stray capacitance, is made such that the gate sidewall is different from the insulating film at the bottom of the overlay described on the left. By protecting the gate metal with an insulating film, the gate metal can be removed without being eroded.
第1図(a)〜(c)は本発明による製法を示す断面図
であシ第1図(ωはオーバレイゲート形成後、第1図(
b)は保護側壁膜形成後、第1図(c)はオーバレイ下
部絶縁膜除去後を示す図である。また第2図はT型ゲー
トの断面図であプ第3図はオーバレイゲートの断面図で
ある。図中の番号は以下のものを表わす。
1 ・・・−Au層、2−−−−−− P を層、3・
・・・・4i層、4・・・−WSi層、5・・・・−3
ift、6・・・・・・5isN、、7・・・・・・ゲ
ート金属、8・・・・・・絶縁膜。
代運人 弁理士 内 原 8 ゛・“′。l
’、 、、:、、’、、i’、)箭1図(θ)
くイシ イ 図 (b)
第1図(C)
第′2′ 区
第3図1(a) to 1(c) are cross-sectional views showing the manufacturing method according to the present invention.
FIG. 1(b) shows the state after the protective sidewall film is formed, and FIG. 1(c) shows the state after the overlay lower insulating film is removed. FIG. 2 is a sectional view of a T-type gate, and FIG. 3 is a sectional view of an overlay gate. The numbers in the figure represent the following. 1...-Au layer, 2-----P layer, 3.
...4i layer, 4...-WSi layer, 5...-3
ift, 6...5isN, 7...gate metal, 8...insulating film. Agent Patent attorney Uchihara 8 ゛・“′.l
', ,,:,,',,i',) 箭 1 fig. (θ) kuishi ii fig. (b) fig. 1 (C) ``2'' section 3 fig.
Claims (1)
素子の形成されるウェハー主平面に第1の絶縁層を形成
する工程と、該第1の絶縁層にゲート電極窓を開口しオ
ーバレイゲートを形成する工程と、前記第1の絶縁層と
は異なる第2の絶縁層を成長する工程と、該第2の絶縁
層をドライエッチングにより異方的にエッチングし、前
記オーバレイゲートのオーバレイ部側壁にのみ前記第2
の絶縁層を残す工程と前記第1の絶縁層を前記第2の絶
縁層を浸食しないエッチング液にてエッチングする工程
を含むことを特徴とするT型ゲートの製造方法。A step of forming a first insulating layer on a main plane of a wafer on which an element is formed in a field effect transistor having a T-type gate structure; and a step of opening a gate electrode window in the first insulating layer to form an overlay gate. , growing a second insulating layer different from the first insulating layer, etching the second insulating layer anisotropically by dry etching, and etching the second insulating layer only on the sidewall of the overlay part of the overlay gate;
A method for manufacturing a T-type gate, comprising the steps of: leaving an insulating layer; and etching the first insulating layer with an etching solution that does not corrode the second insulating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8151387A JPH0666337B2 (en) | 1987-04-01 | 1987-04-01 | Method for manufacturing T-type gate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8151387A JPH0666337B2 (en) | 1987-04-01 | 1987-04-01 | Method for manufacturing T-type gate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63245961A true JPS63245961A (en) | 1988-10-13 |
JPH0666337B2 JPH0666337B2 (en) | 1994-08-24 |
Family
ID=13748426
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8151387A Expired - Lifetime JPH0666337B2 (en) | 1987-04-01 | 1987-04-01 | Method for manufacturing T-type gate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0666337B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5869365A (en) * | 1996-10-03 | 1999-02-09 | Nec Corporation | Method of forming T electrode in field effect transistor |
US5981359A (en) * | 1996-10-21 | 1999-11-09 | Nec Corporation | Method of manufacturing semiconductor device having isolation film on SOI substrate |
-
1987
- 1987-04-01 JP JP8151387A patent/JPH0666337B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5869365A (en) * | 1996-10-03 | 1999-02-09 | Nec Corporation | Method of forming T electrode in field effect transistor |
US5981359A (en) * | 1996-10-21 | 1999-11-09 | Nec Corporation | Method of manufacturing semiconductor device having isolation film on SOI substrate |
Also Published As
Publication number | Publication date |
---|---|
JPH0666337B2 (en) | 1994-08-24 |
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