JPS63127589A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve yield on the manufacture of mesa type devices by executing a step in which an opening is formed at the top section of a mesa to an insulating film for constricting currents in a self-alignment manner. CONSTITUTION:Mesa etching is conducted by using a mask consisting of multilayer films 6, 7, 8, and a insulaing film for constricting currents is applied onto the whole surface of a substrate under the state in which the mask is left. A material is selected previously so that the chemical etching rate of the insulating film is made sufficiently smaller than the etching rate of any film in the multilayer films at that time. When chemical etching is performed under the state, an etchant starts intrusion from the incomplete position of the coating of the insulating film in an undercut section in the multilayer films employed as the mask, and lastly a dielectric layer 7 as a second layer can be removed perfectly while a dielectric layer 6 as a first layer is also got rid of, thus exposing only the top section of a mesa. The insulating film for constricting currents is not taken off because it is difficult to etch at that time. Consequently, an opening can be bored in a self-align-ment manner at the top section of the mesa to the insulating film 11 for constricting currents. Accordingly, the lowering of yield on manufacture due to the positional displacement of the opening can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming electrodes during the manufacturing process of a semiconductor device having a mesa-shaped (trapezoidal) structure.

[Conventional technology]

In general, mesa structures are widely used in semiconductor devices because they are effective in improving response characteristics by reducing parasitic capacitance or suppressing current spread. In an element having this mesa structure, one electrode is usually provided at the top of the mesa.

An example of a method for forming this mesa structure will be explained with reference to FIG. Here, a ridge waveguide type semiconductor laser using an InP substrate is shown as an example (Magazine [Electronics Letters)]
ers)j, vo I, 15. No. 23
(1979), PP 763-65).

First, in Figure 2 (a), an n-type InP substrate is
Type InP buffer layer 2. InGaAsP active layer 3. r)
After epitaxially growing the InP-type cladding layer 4 and the p-type InGaAsP capping layer 5, as shown in FIG.
In b), after providing a mask 14 made of photoresist, metal or dielectric, a mesa structure is formed by etching. Next, after removing the mask 14, the second
In Figure (c), the entire surface of the substrate is covered with an insulating film 15. Thereafter, in FIG. 2(d), an opening 17 is formed in the photoresist film 16 at the top of the mesa by photolithography, and an opening 17 is also formed in the insulating film 15 by etching. After that, the photoresist film 16 was removed and an n-type ohmic electrode 12 was formed on the surface of the substrate having a mesa structure.
After polishing the n-type (InF) substrate 1, an n-type ohmic electrode 13 is formed to complete the manufacturing process (FIG. 1(e)).

[Problem that the invention seeks to solve]

When attempting to selectively form an electrode on the top of a mesa using this conventional technique, alignment exposure is performed on the photoresist film 16 coated on the insulating film 15, as shown in FIG. It is necessary to selectively remove the photoresist film 16 at the top. However, the tolerance value for positional deviation during alignment exposure requires that the edge of the aperture 17 not protrude from the top of the mesa, as well as the requirement for stability of the transverse mode during laser oscillation. On the other hand, an accuracy of ±1 to 2 μm is required.

In manufacturing devices having a mesa structure as described above, strict conditions of approximately ±1 to 2) tm may be required for the opening position accuracy required to selectively form electrodes on the top of the mesa. In many cases, this is a major cause of lowering device manufacturing yield.

An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates such drawbacks and significantly improves the manufacturing yield of mesa-type devices by forming electrodes in a self-aligned manner on the top of the mesa. be.

[Means for solving problems]

The structure of the present invention is a method for manufacturing a semiconductor element having a mesa structure on the surface of a semiconductor substrate, wherein a first dielectric film is provided on the surface of the substrate, and the chemical etching rate is higher than that of the first dielectric film. a step of sequentially depositing a second dielectric film and a third dielectric film having a chemical etching rate equivalent to that of the first dielectric film; and a step of depositing a photoresist on the third dielectric film. selectively etching and patterning only each of the dielectric films using reactive ion etching as a mask; a step of providing an undercut portion in the second dielectric film by chemical etching; forming a mesa-type structure on the substrate surface by etching after removing the resist; covering the substrate surface with an insulating film having a lower chemical etching rate than the first dielectric film; removing the second and first dielectric films by chemical etching using etching seepage from the undercuts 1 to 1 provided in the dielectric film of the mesa to expose only the top portion of the mesa. Features.

[Effect]

In the present invention, a multilayer film consisting of three dielectric films is used as a mask in the mesa etching process of a semiconductor substrate. The layer film has an undercut. After mesa etching is performed using a mask made of such a multilayer film, an insulating film for current confinement is deposited over the entire surface of the substrate with the mask remaining. At this time, the material should be selected so that the chemical etching rate of the insulating film is sufficiently lower than the etching rate of any film in the multilayer film. When chemical etching is performed in this state, the etchant begins to penetrate through the incomplete coverage of the insulating film at the undercut portion of the multilayer film used as a mask, and eventually the second layer dielectric layer is exposed. The body layer can be completely removed, and the first dielectric layer is also removed, exposing only the top of the mesa. At this time, the insulating film for current confinement is not removed because it is difficult to be etched.

As described above, in the present invention, when manufacturing a semiconductor device having a mesa structure, the step of forming an opening at the top of the mesa in the insulating film for current confinement can be performed in a self-aligned manner. Thus, it is possible to avoid a decrease in manufacturing yield due to the positional deviation of the opening.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 1(a) to 1(f) are device cross-sectional views showing an example of the method for manufacturing a semiconductor device having a mesa structure according to the present invention in the order of steps. An example is shown.

First, in FIG. 1(a), an n-type InP substrate 1 is
Type 1nP buffer layer 2. InGaAsP active layer 3. A p-type InP cladding layer 4 and a ρ-type InGaAl5P cap layer 5 are epitaxially grown continuously. Next, the first
In Figure (b), a first dielectric film 6. After the second dielectric film 7 and the third dielectric film 8 are sequentially deposited, a photoform with a thickness of about 2 μm is patterned to have a width of about 5 to 15 μm by photolithography on the surface of the third dielectric film 8. Reactive ion etching is performed using the resist film 9 as a mask. The second and first dielectric films 8.7 and 6 are patterned. Subsequently, chemical etching is performed to provide an undercut portion 10 in the second dielectric film 7 by utilizing the difference in etching speed.

At this time, the first. In selecting the materials constituting the second and third dielectric films 6.7 and 8, the photoresist 15I
In active ion etching using 9 as a mask, care must be taken so that all dielectric films can be etched quickly even under conditions in which the p-type 1nGAAsP cap layer 5 is not etched. In addition, in chemical etching using the photoresist film 9 as a mask, p-type I
Under the condition that the nGaAsP cap layer 5 is not etched, the etching rate of the second dielectric film 7 is the same as that of the first and third etching rates.
Care should be taken to make it larger than the dielectric film.

Specific examples of such dielectric films include the following.

The first dielectric film 6 can be formed using a sputtering method or a relatively high temperature (
450℃) formed by thermal CVD method with a thickness of 0.2
The second dielectric film 7 is a PSG film with a thickness of about 0.2 μm, which is formed by thermal CVD at a low temperature (about 310° C.) and contains about 8% P (phosphorus) by weight.
(Pbospbosilicate glass) membrane,
As the third dielectric 1118, 5i02 with a thickness of about 0.2 μm formed by the same method as the first dielectric film 6 can be used.

The reactive ion etching conditions include CF, +
By using 82 or CHF3 gas, the etching rate of any dielectric film can be made approximately one times the etching rate of the photoresist film 9, which is a mask, so that etching can be performed without destroying the mask. Further, the p-type nGaAsP cap layer 5 is not etched under these conditions.

Next, the chemical etching conditions for forming the undercut portion 10 in the second dielectric film 7 (material: PSG) will be described.
If a mixed solution of F and NH4F is used, PS
Since the chemical etching speed of G is about 4 times higher than that of 5i02, the undercut portion 10 with a width of about 1 to 2 μm is
It is relatively easy to provide. At this time p-type 1 nG
The aAsP cap layer 5 is not etched.

When the chemical etching is completed, the photoresist film 9 is removed and the process moves to the next step shown in FIG. 1(c).

In this step, the semiconductor substrate 1 is etched using a mask made of three layers of dielectric films, and chemical etching using a mixed solution of bromine and methanol can be used as the etching method. At this time, the three-layer dielectric mask is not etched. Next, Figure 1 (
In d), the entire surface of the substrate including the mesa structure is covered with an insulating film 11 for current confinement while leaving the dielectric mask intact.

At this time, the insulating film 11 is interrupted at the undercut portion 10 due to a large step difference. When selecting the material constituting the insulating film 11, consideration should be given so that the chemical etching rate for an etchant that is limited to not etching the p-type InGaAsP layer 5 is sufficiently lower than the etching rate for any of the dielectric films. be done.

As a specific example of this, SiNx with a thickness of about 0.3 μm formed by plasma CVD at a formation temperature of about 300° C. can be used as the insulating film 11. At this time, the chemical etching rate with respect to the buffered hydrofluoric acid described above is the same as that of SiO□ as a specific example of the first dielectric film 6.
It is possible to reduce the amount by 1/10 or less.

Next, in the step of FIG. 1(e), chemical etching (
Specific etchants include buff art and hydrofluoric acid)
The second dielectric film 7 is then removed by removing the first dielectric film [6] by utilizing the seepage of Elachan I from the undercut portion 10 to expose only the top of the mesa. can. At this time, the insulating film 11 is not easily etched and is not removed. Finally, a p-type ohmic electrode 12 is placed on the surface of the substrate having a mesa structure in FIG.
After forming, the n-type InP substrate 1 is polished, and the rl-type ohmic electrode 13 is formed to complete the manufacturing process.

[Effects of the Invention] As explained above, according to the present invention, in manufacturing a semiconductor device having a mesa structure, the step of forming an opening at the top of the mesa in an insulating film for current confinement can be performed in a self-aligned manner. Therefore, it is possible to avoid a decrease in manufacturing yield due to positional deviation of the opening, which was a problem in the prior art.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views showing an embodiment of the present invention in the manufacturing process of a mesa-type semiconductor device, and FIGS. 2(a) to (e)
) is a cross-sectional view showing a conventional method for manufacturing a mesa-type semiconductor device in the order of steps. DESCRIPTION OF SYMBOLS 1...n-type InP substrate, 2...n-type InP buffer layer, 3--InPGaAsP active layer, 4-P-type InP cladding layer, 5...p-type 1nGaAsP cap layer, 6
... first dielectric film, 7... second dielectric film, 8.
...Third dielectric film, 9.16... Photoresist film, 10... Undercut portion, 11.15... Insulating film, 12... P-type ohmic, 13... N-type Ohmic electrode, 14...mask, 17... opening. Bamboo shoot once

Claims (1)

[Claims] In a method of manufacturing a semiconductor device having a trapezoidal mesa structure on the surface of a semiconductor substrate, a first dielectric film is provided on the surface of the substrate, and a second dielectric film having a higher chemical etching rate than the first dielectric film is provided on the surface of the substrate. A step of sequentially depositing a dielectric film and a third dielectric film having a chemical etching rate equivalent to that of the second dielectric film, and using a photoresist provided on the third dielectric film as a mask. A step of selectively etching and patterning only each dielectric film by reactive ion etching, a step of providing an undercut portion in the second dielectric film by chemical etching, and etching after removing the photoresist. forming a mesa structure on the surface of the substrate by
covering the substrate surface with an insulating film having a lower chemical etching rate than the second dielectric film; 1. A method for manufacturing a semiconductor device, comprising the step of removing the dielectric film of No. 1 by chemical etching to expose only the top portion of the mesa.