JPS6149249A - Interleave control system of memory device - Google Patents

Abstract

PURPOSE:To attain the address interleave between memories of different capacities by providing an address interleave flag every unit capacity to the memories to which independent access is possible and then converting a real address into a physical address. CONSTITUTION:An address conversion mechanism 3 converts the real addresses for memory access given from a central processor and a channel controller into the physical addresses of a main memory. An address interleave flag 1 consisting of plural bits is provided to the mechanism 3 every unit capacity of memories of different capacities to which access is possible independently of each other and which constitute a main memory. Then the least significant bit of an address in a segment is replaced with the least significant bit of a segment number and an upper address in the segment. Thus an address interleave operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address translation method that enables address interleaving between storage devices having different storage capacities.

With the recent remarkable progress in semiconductor technology, the degree of integration of memory elements constituting the main memory device has improved, and as the capacity of the main memory 5 device has increased, the capacity of each expansion unit has also become larger.

On the other hand, due to the diversification of the usage patterns of data processing systems on the user side and the trend toward economicalization, the optimal storage system for each user has become required, and storage devices with arbitrary capacities can be installed. As a result, it has become necessary to respond to user preferences.

However, in order to improve the throughput of a data processing system, storage systems generally provide n
Access is possible using the way interleaving method, but if the address interleaving method cannot be utilized by adding storage devices of different capacities, there is a problem that serviceability for users will deteriorate.

In view of these circumstances, there has been a demand for an interleaving control method that enables address interleaving even between main storage devices configured with storage devices with different storage capacities and that does not reduce the performance of the data processing system.

[Conventional technology]

Generally, in a data processing system, a central processing unit,
When accessing main storage from a channel controller,
Each device performs logical address to real address conversion, and the storage control device intervening between the main storage device converts the real address to a physical address, which is accessed independently of each other in segments called segments. possible,
In addition, a fixed capacity access unit is accessed using a one-way increment method or an n-way increment method.

FIG. 3 is a diagram explaining the concept of the memory access method using the conventional interleaving method, in which (a) is a diagram schematically showing the configuration of the memory system, and (b) is a diagram schematically showing the configuration of the memory system. Fig. 3 is a diagram illustrating the address translation mechanism in , where (a) shows a floating memory address (hereinafter referred to as FiIA) mechanism [to a real address] physical address translation mechanism] 3, and (b) shows the above-mentioned FMA i structure 3.
A floating memory address word (hereinafter referred to as FMAW) 31 is shown.

First, in the memory system shown in (a), one segment consists of four 4MB memory units, and there are eight segments each consisting of four memory units, for a total of 32 memory units (i.e., 1
Each memory unit is selected by a 5-bit physical address consisting of a segment number and an upper address within the segment.

The above Fl'lA3 is composed of 32 words FMAWO to r'MAW31, which is the same number as the number of memory units mentioned above, and by accessing 3gFMA3 using the upper 5 bits of the above real address as the FMA search address, The above-mentioned physical addresses set in FMIVO to FMAW 31 can be obtained from the real address.

As shown in (b) of (b), the above 5-bit physical address includes a segment number (SEG'NO),
It consists of upper addresses in the segment (SEG upper 8 D), and by setting the contents of the FMAW 31 in the FMA 3 above in advance in correspondence with each real address, any segment can be set to 1. Way or n
It can be accessed by way interleaving method.

In the conventional method, in order to improve the throughput of a memory system constructed of multiple storage devices (segments) that can operate independently from each other, the above method is used to: ■ access the multiple segments in parallel; Method.

(2) A method of incrementing the memory access address for the plurality of segments to equalize the access frequency of each segment.

One of the following methods was used.

[Problem that the invention seeks to solve]

In the address interleaving method described in item (2) above, the plurality of segments must all have the same storage capacity (2), and there is a problem in that the unit of expansion becomes large. Furthermore, if the storage capacity differs for each segment, effective address interleaving becomes impossible, resulting in the problem that performance cannot be improved.

Also, in the parallel access method described in item (2), the capacity of the segments is fixed, and there is a problem that segments with different storage capacities cannot be accessed.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a method that enables address interleaving between storage devices (segments) having different storage capacities.

[Means for solving problems]

The purpose of this is: (1) For each unit capacity (memory unit) of the storage devices (segments) that make up the main storage device that can be accessed independently from each other, the real address → physical address conversion mechanism provided in the storage control device is used. , an address interleave flag is provided, and the flag indicates.

Address interleaving can be performed by converting a real address converted according to an interleaving instruction into a physical address for memory access.

(2) The address interleave flag is composed of multiple focus points, and allows 2n-way (n≧0) address interleaving to be set.

This is achieved by the storage device increment control method of the present invention.

[Effect]

That is, according to the present invention, an address conversion mechanism (to close) that converts real addresses for memory access from the central processing unit and channel control unit into physical addresses of the main storage device,
For each unit capacity (for example, 4 MB) of storage devices (segments) that can be accessed independently and have different storage capacities, which constitute the main storage device, an address increment flag consisting of multiple bits is provided. Depending on what the flag indicates, the least significant bit of the intra-segment address is
The segment number and the least significant bit of the upper address within the segment are exchanged to enable address-in-leap, so address interleaving between storage devices with different storage capacities is possible, and data This has the effect of improving the performance of the processing system and reducing the size of the expansion unit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a diagram schematically showing an embodiment of the present invention.

Figure 1 (a) shows a memory system with a total of 128 MB, which has 4 memory units each with a unit capacity of 4 MB, and 8 segments of the storage device that constitutes one segment, as explained in Figure 3 (a). By implementing the present invention, N segments/M
The above-mentioned FM when configuring the memory system of the
Examples of the segment number (SIEG NO) of AW31 and the upper address within the segment (SEG upper AD) are shown for cases where the storage capacity is 32 MB and 64 MB.

The above N segment is denoted by N SEG, and the M way is denoted by M.
In terms of WAY, (2) shows the relationship between the above SEG NO and the SEG upper AD when the storage capacity is 32 MB with 2 SEC/1 8 Y.

Hereafter, in the same way, ■ is ';, SEG/2 side y
If the storage capacity is 32MB, ■ is 4 SEG/2 W
If the storage capacity is 64MB in ^Y, ■ is 4 SEG/4
It is easy to understand that the figures show the case where the memory capacity is 61c in 1st AY.

This means that an N-segment/M-way memory system can generally be configured by arbitrarily setting the contents of the FMAW 31 described above.

Figure 1 (b) schematically shows how to generate real addresses when constructing the above memory system.
) indicates valid bits 5 to 31 of the real address,
The upper 26 to 31 bits are the in-block byte address, and the 5 to 25 bits are the real address in block units.

(b) of this figure shows an example of real address conversion when implementing the present invention. For example, in the case of 2-way, the number of bytes in a block is 64 bytes, so from segment number +01 When the access for the 64 bytes is completed for the first time, the next byte address needs to move to segment number "1", so the 25th and 9th bits are
It can be seen that 2-way address incremental access can be realized by exchanging the bits.

Similarly, in the case of 4-way, it can be realized by exchanging the 8.9th bit and the 24.25th bit.

Furthermore, in this embodiment, the top 5 of the converted real addresses are
Bits are used as the search address of the FMA 3, and the physical address for the storage device is determined by the segment number obtained from the FMAW 31, which is the content of the PMA 3, and the upper address within the segment. Upper address within segment (SE
G upper AD) and lower address within the segment (10~
The intra-segment address of any segment can be specified using

FIG. 2 shows the present invention in which segments (S
An example is shown in which it is applied to a memory system consisting of EGO to 5EG3), and (a) shows the configuration of the memory system, which is a segment.

0' (SEG O) has a capacity of 4 x 4MB,
Segment "1° (SEG 1) has a capacity of 2 x 4MB, segments "2' and '3° have a capacity of I
It is assumed that the memory units have a capacity of 4 MB, and the numbers (0 to 7) assigned to the memory units each having a unit capacity of 4 MB indicate the order in which data is stored.

In this case, if you try to access the order in which the data is arranged, the first 0 to 3 units will be accessed 7 times using a 4-way interleaving method, and the next 4 or 5 units will be accessed in a 2-way step. The remaining 6 and 7 units must be accessed in 1-way.

(b) is 1'M^ when realizing the above memory access
This shows an example of setting FMAW31 in No. 3 (a) and an example (b) of the above-mentioned bit conversion of the real address.
By using the real address after conversion shown in (a), it becomes possible to increment addresses for the storage devices with different storage capacities shown in (a).

Here, without further explanation (the conversion in (b) above is exactly the same as the conversion method explained in Figure 1 (b),
The position of the X mark at 8 and 9 bits of the real address is controlled to be replaced with the position of the 24.25 bit of the real address.

FIG. 2(c) schematically shows the real address conversion method for searching for FMA 3 explained in (b) above, where 1 is the unit capacity (in this example), which is the main focus of the present invention. So, 4
This figure shows an example of the address interleave flag provided for each 4MB memory unit (MB), which is the constituent unit of this memory system, as shown in this example.
A total of 32 flags) are provided with an increment flag (FMA FLAG) i structure 1 for each memory unit.
The required number of interleaving ways may be indicated for each node.

Interleaving flag (FMA PLAG) 1 like this
In order to search for the above 32 memory units, the upper 5 bits of the real address are accessed, and based on the obtained flag information (for example, the number of interleave ways), each interleave way is Therefore, correspondingly, the conversion of the real address explained in FIG. By using an address, it becomes possible to perform address increment between storage devices (segments) having different storage capacities, which is the intended purpose.

〔Effect of the invention〕

As described above in detail, the interleave control method for a storage device of the present invention uses an address translation mechanism (FMA) that converts real addresses for memory access from the central processing unit and channel control device into physical addresses of the main storage device. ) 3
An address interleave flag consisting of a plurality of bits is provided for each unit capacity (for example, 4 MB) of storage devices (segments) that can be accessed independently and have different storage capacities that constitute the main storage device, Depending on the content indicated by the flag, the least significant bit of the address within the segment is replaced with the least significant bit of the segment number and the upper address within the segment, allowing for address interleaving. It becomes possible to perform address ink and leave between storage devices with capacity, which has the effect of improving the performance of the data processing system and reducing the unit of expansion.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the present invention in detail, FIG. 2 is a diagram schematically showing an embodiment of the present invention, and FIG. 3 is a diagram explaining a conventional address interleave control method. In the drawing, 1 is an interleave flag (FMA-FLAG). 2 is a real address converter. 3 is a real address to physical address converter (PMA). 31 is floating memory address word (1'M8w)
. SEG NO is the segment number. SεG upper ΔD is the segment upper address. are shown respectively. (α) (b) FMA-FLA (f 2 ward 3 1q (a) no 31iiJ (b)

Claims (2)

[Claims] (1) In a storage system equipped with a function of converting a real address for memory access from a central processing unit or a channel control unit into a physical address to a main storage device, the main storage device is configured with the address conversion function. Address interleaving is performed by providing an address interleaving flag for each unit capacity of a storage device (segment) that can be accessed independently, and converting the real address converted according to the interleaving instruction indicated by the flag into a physical address for memory access. An interleave control method for a storage device, which is characterized in that it enables the following. (2) The storage device according to claim 1, wherein the address interleaving flag is composed of a plurality of bits, and is configured to set 2^n-way (n≧0) address interleaving. interleave control method.