JPS6148937A - Deviding method of semiconductor wafer - Google Patents

Deviding method of semiconductor wafer

Info

Publication number
JPS6148937A
JPS6148937A JP59171105A JP17110584A JPS6148937A JP S6148937 A JPS6148937 A JP S6148937A JP 59171105 A JP59171105 A JP 59171105A JP 17110584 A JP17110584 A JP 17110584A JP S6148937 A JPS6148937 A JP S6148937A
Authority
JP
Japan
Prior art keywords
unit element
wafer
element parts
semiconductor wafer
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59171105A
Other languages
Japanese (ja)
Inventor
Akihisa Taniguchi
谷口　明久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59171105A priority Critical patent/JPS6148937A/en
Publication of JPS6148937A publication Critical patent/JPS6148937A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To improve a product yield by surrounding a wafer in every group of scheduled unit element portions with dicing lines and deviding into chips. CONSTITUTION:Multiple unit element portions 2 are formed on a wafer 1. A dicing line 11 is formed by surrounding each four unit element portion. The line 11 is formed by using a characteristic mask in a photolithography of a glass coat of the uppermost layer of the wafer 1. Surrounded with the lines 11, this can be found to be one chip at a glance and a needle of a probe card is just set to this. In order to devide the wafer in succession, the wafer is notched along the line 11 with a cutter device and devided in the latter process.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、形成された多数の単位素子部を、複数の単
位素子部ごとにまとめたチップ宛に分割するようにする
。半導体ウェーハの分割方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] According to the present invention, a large number of formed unit element parts are divided into chips each of which is grouped into a plurality of unit element parts. This invention relates to a method for dividing a semiconductor wafer.

〔従来技術〕[Prior art]

例えば、高周波高出力トランジスタなど半導体素子用の
単位素子部が多数配列形成された半導体ウェーハ（以下
「ウェーハ」と称する）では、従来１分割する前に各単
位素子部を全数にわたりオートテストを行う、これには
、１個の単位素子部に２木の測定用針をエミッタの電極
部とペースの電極部とに接触させ、検査をし良否の判定
を行っていた。しかし、これでは全数検査に多大の時間
がかかつていた。For example, in the case of a semiconductor wafer (hereinafter referred to as a "wafer") in which a large number of unit element parts for semiconductor devices such as high-frequency, high-output transistors are formed in an array, an automatic test is conventionally performed on all unit element parts before dividing into one. To do this, two wooden measuring needles were brought into contact with the emitter electrode and the pace electrode in one unit element part, and the inspection was performed to determine the quality. However, this required a large amount of time to conduct a complete inspection.

近来、半導体素子の高出力化に伴って、近接した単位素
子部を所要数分まとめて、大チップとして分割し、各単
位素子部を並列接続して１個の半導体装置として使用す
るようになってきた。In recent years, as the output of semiconductor devices has increased, it has become possible to group together the required number of adjacent unit element parts, divide them into a large chip, and connect each unit element part in parallel to use it as a single semiconductor device. It's here.

このため、ウェーハに対し、プローブカードと云はれて
いる試験装置で、多数の測定用針によシ複数の単位素子
部を同時に測定するよってなった。For this reason, it has become necessary to simultaneously measure a plurality of unit element parts on a wafer using a test device called a probe card using a large number of measuring needles.

この場合、不良の単位素子部にはインクを付着し表示し
なければならない、しかし、単位素子部の寸法は非常に
小さく、インクを個々の不良チップ邪に打っていたので
は、インクを出す各インク付Ｎ具が相互に当ってしまう
ので１個々には打つことはできない。そこで、インク付
着具を１ｍ用い、ウェーハをファセット（外周の切欠き
ｇＳ）を下にして、所要数分の単位素子部をまとめて、
そのうち、不良単位素子部があれば、そのまとめた単位
素子部群の右端又は左端のいづれかに決めてインクを付
着し、その約束に従ってダイシングをしていた。この場
合１例えば左端の単位素子部にインクを付着するように
しておくと、２個の単位素子部をまとめて判定したとき
、否、良と続くと４個の単位素子部の否と同じ状態とな
り、ダイシングする際に４個の単位素子部を一体として
切るところを、２個の単位素子部を一体として切ってし
まい、仕損じ品を出すおそれがあった。In this case, it is necessary to apply ink to the defective unit element to display an indication.However, the dimensions of the unit element are very small, and if ink is applied to each defective chip, it will be difficult to apply ink to each defective chip. Since the ink-covered N tools touch each other, they cannot be applied individually. Therefore, using an ink adhesion tool of 1 m, the wafer was placed with the facet (notch gS on the outer periphery) facing down, and the required number of unit element parts were assembled.
If there was a defective unit element part among them, ink was applied to either the right end or the left end of the assembled unit element part group, and dicing was performed according to the agreement. In this case 1, for example, if ink is applied to the leftmost unit element part, when two unit element parts are judged together, if the result is "No" and then "Good", the same state as that of the four unit element parts will be obtained. Therefore, when dicing, instead of cutting four unit element parts as one unit, two unit element parts are cut as one unit, and there is a risk of producing rejected products.

また、ウェーハの一部が分割されて残った部分にファセ
ットのない状態になると、ウェーハのファセットを下の
位置にして決めた。不良マークを単位素子部群の右端又
は左端て付着した基準がわからなくなり間違いが生じる
。これをなくするには、いちいち図を書いて指示をして
おかねばならなかった。Also, when a portion of the wafer was divided and the remaining portion had no facets, the facets of the wafer were placed in the lower position. Mistakes occur because the reference mark attached to the right or left end of the unit element group becomes unclear. In order to eliminate this, I had to draw diagrams and give instructions one by one.

従来のウェーハの分割方法は、第１図にウェーハの一部
を平面図で示すようにしていた。（１）はウェーハで、
多数個の同一の単位素子部（２）が形成されている。（
３）は各単位素子部（２）間に入れられ、基盤目状に形
状されたダイシングラインで、最上層のガラス被膜を写
真製版する際、共通のマスクを用いて形成する。In the conventional method of dividing a wafer, a part of the wafer is shown in a plan view as shown in FIG. (1) is a wafer,
A large number of identical unit element parts (2) are formed. (
3) is a dicing line that is inserted between each unit element part (2) and shaped like a base grid, and is formed using a common mask when photoengraving the top layer glass film.

こうして、ウェーハ（１）はオートテスト後、単位素子
部（２）を必要個数分ごとまとめて分割できる利点はあ
る。しかし、実際には、ウェーハ（１）を何に使用する
かによシ、オートテストの規格で何個分まとめて１チツ
プとして分割することが決まってしまい、他への転用は
無理な場合が多く、利点とはなυ難く、上記のような欠
点が生じていた。In this way, the wafer (1) has the advantage of being able to be divided into the necessary number of unit element parts (2) after the auto-test. However, in reality, depending on what the wafer (1) is used for, the autotest standard determines how many wafers must be divided into one chip, and it may not be possible to use it for other purposes. In many cases, there were disadvantages such as those mentioned above, rather than advantages.

〔発明の概要〕[Summary of the invention]

この発明は、上記従来のウェーハの分割方法の欠点をな
くするためになされたもので、ウエーノ・の上面に、所
要数の単位素子部ごとにまとめて囲うダイシングライン
を形成し、このダイシングラインに沿って分割すること
だよシ、所要の個数の単位素子部が一体になったチップ
が得られるようにし、誤って違う個数の単位素子部ごと
にして分割することを防ぎ、製品歩留りを向上する。ウ
ェーハの分割方法を提供することを目的としている。This invention was made in order to eliminate the drawbacks of the conventional wafer dividing method, and involves forming a dicing line on the upper surface of the wafer that encloses the required number of unit element parts, and It is necessary to divide the chips along the same line, so that a chip with the required number of unit element parts is integrated, prevents the chip from being divided into the wrong number of unit element parts by mistake, and improves product yield. . The purpose is to provide a method for dividing wafers.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例によるウェーハの分割方法を
、第２図に示すウェーハの一部の平面図によｐ説明する
。ウェーハ（１）には多数個の単位素子部（２）が形成
されている。６℃は所要数（図では４個）の単位素子部
（２）ととＫまとめて囲って形成されたダイシングライ
ンで、ウェーハ（１）の最上層のガラス被膜を写真製版
する際に固有のマスクを用いて形成する。Hereinafter, a method for dividing a wafer according to an embodiment of the present invention will be explained with reference to a plan view of a portion of a wafer shown in FIG. A large number of unit element parts (2) are formed on the wafer (1). 6°C is a dicing line formed by enclosing the required number (4 in the figure) of unit element parts (2) and K, and is a dicing line formed by enclosing the required number (4 in the figure) of unit element parts (2). Form using a mask.

上記単位素子部（２）を形成する写真製版のマスクは、
すべて共通のものでよい。The photolithography mask forming the unit element portion (2) is:
All should be common.

こうして、必要数の単位素子部（２）をまとめてダイシ
ングラインαＤで囲っているので、これが１チップにな
ることが一目でわかり、これにブローン。In this way, since the required number of unit element parts (2) are grouped together and surrounded by the dicing line αD, it can be seen at a glance that this is one chip, and this is blown.

カードの針を合わせればよい、つづいて、分割するには
、ダイシングラインα℃に沿ってカッタ装五で切込みを
入れ、後工程で分割する。All you have to do is align the needles of the card. Next, to divide the card, make a cut with a cutter along the dicing line α°C, and divide it in a later process.

これにより、所要数１例えば４個の単位素子部（２）ご
とに切るのを１間違って２個の単位素子部（２）で切っ
てしまうことが防止される。また、たとえ間違って切っ
たとしても、そこには酸化膜があり。This prevents cutting into two unit element parts (2) by mistake when the required number, for example, four unit element parts (2) are cut. Also, even if you cut it by mistake, there is an oxide film there.

切込むことができず１分割というウェーハ製作の最終工
程でロット仕損による大きな損失がなくなる。さらに、
最終工程でまとめて切る単位素子部（２）の数を決める
ことにより、ウェーハ（１）の用途への振向けの際便利
である。This eliminates large losses due to lot rejects in the final process of wafer production, where cutting is not possible and the wafer is divided into one piece. moreover,
By determining the number of unit element parts (2) to be cut at once in the final process, it is convenient to allocate the wafer (1) to the intended use.

〔発明の効果〕 以上のように、この発明の方法によれば、ウェーハに所
要数の単位素子部ごとにまとめてダイシングラインで囲
い、このダイシングラインに沿って切込みを入れ、チッ
プに分割するようにしたので、間違った個数の単位素子
部ごとに分割する仕損じが防止され、製品歩留シが向上
される。また、ウェーハの一部が分割され７アセツト部
が除かれた場合でも、所要数の単位素子部が一目でわか
り。[Effects of the Invention] As described above, according to the method of the present invention, a wafer is surrounded by a dicing line for each required number of unit element parts, and cuts are made along the dicing line to divide it into chips. Therefore, it is possible to prevent waste caused by dividing into the wrong number of unit element parts, and improve product yield. Furthermore, even if a part of the wafer is divided and seven asset parts are removed, the required number of unit element parts can be seen at a glance.

不良品マークによる判断に困ることはなく、作業性が向
上される。There is no problem in making judgments based on defective product marks, and work efficiency is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のウェーハの分割方法を示すウェーハの一
品の平面図、第２図はこの発明の一実施例によるウェー
ハの分割方法を示すウェーハの一部の平面図である。 １・・・半導体ウェーハ、２・・・単位素子部、１１・
・・ダイシングラインFIG. 1 is a plan view of one piece of a wafer showing a conventional wafer dividing method, and FIG. 2 is a plan view of a part of a wafer showing a wafer dividing method according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... Unit element part, 11.
・Dicing line

Claims (2)

【特許請求の範囲】[Claims] （１）多数の単位素子部が形成された半導体ウェーハの
面に、所要数の上記単位素子部ごとにまとめて囲うダイ
シングラインを形成し、このダイシングラインに沿つて
切込み加工をし、上記所要数の単位素子部を一体にした
チップ宛に分割する半導体ウェーハの分割方法。(1) On the surface of a semiconductor wafer on which a large number of unit element parts have been formed, a dicing line is formed to surround each of the required number of unit element parts, and cuts are made along this dicing line, and the required number of unit element parts are A semiconductor wafer dividing method in which the unit element parts of the semiconductor wafer are divided into chips. （２）半導体ウェーハの最上層のガラス被膜を写真製版
する際に、マスクを用いダイシングラインを形成する特
許請求の範囲第１項記載の半導体ウェーハの分割方法。(2) The method for dividing a semiconductor wafer according to claim 1, wherein a mask is used to form dicing lines when photoengraving the uppermost glass coating of the semiconductor wafer.
JP59171105A 1984-08-16 1984-08-16 Deviding method of semiconductor wafer Pending JPS6148937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59171105A JPS6148937A (en) 1984-08-16 1984-08-16 Deviding method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59171105A JPS6148937A (en) 1984-08-16 1984-08-16 Deviding method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS6148937A true JPS6148937A (en) 1986-03-10

Family

ID=15917064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59171105A Pending JPS6148937A (en) 1984-08-16 1984-08-16 Deviding method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS6148937A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008095514A (en) * 2006-10-06 2008-04-24 Mitsubishi Heavy Ind Ltd Load-restriction operation method and device of engine during misfire

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008095514A (en) * 2006-10-06 2008-04-24 Mitsubishi Heavy Ind Ltd Load-restriction operation method and device of engine during misfire

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