JPS6148793B2 - - Google Patents
Info
- Publication number
- JPS6148793B2 JPS6148793B2 JP54090786A JP9078679A JPS6148793B2 JP S6148793 B2 JPS6148793 B2 JP S6148793B2 JP 54090786 A JP54090786 A JP 54090786A JP 9078679 A JP9078679 A JP 9078679A JP S6148793 B2 JPS6148793 B2 JP S6148793B2
- Authority
- JP
- Japan
- Prior art keywords
- misfet
- misfets
- composite
- unit
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002131 composite material Substances 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は互いにしきい値電圧の差の極めて小
さい絶縁ゲート電界効果トランジスタ対の構成に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a pair of insulated gate field effect transistors having an extremely small difference in threshold voltage.
互いにしきい値電圧の差の極めて小さい絶縁ゲ
ート電界効果トランジスタ（MISFETと略称す
る。）の対は差動増幅器の入力回路などに広く要
求されている。MISFETのしきい値電圧Ｖthは
Ｖth＝φMS−（ＱSS／Ｃp）±（ＱB／Ｃp）
＋２φF
で与えられる。こゝで、
φMS：基板材料と電極材料と仕事関数の差
ＱSS：表面準位密度
ＱB：基板の電荷密度（符号の正負は伝導形によ
つてきまる。）
φF：フエルミ関数
ＣO：チヤネル領域上の絶縁膜による容量
である。上式中でφMSおよびφFは基板材料と電
極材料とによつて一義的に決まるもので、同じ基
板上に構成されたMISFET対のしきい値電圧に
差異を生じさせる要因はＱSSとＱBとになる。す
なわち、同一基板であつても、その位置によつ
て、また形状の不平衡によつてこれらの値に差異
を生じるからである。そこで、これらの不平衡原
因の影響を避けるために、１枚の基板上に４個の
単位MISFETを形成し、その内の第１群の２個
を並列にして構成したMISFETと、残りの第２
群の２個を並列にして構成したMISFETとを対
として用いる方式が用いられている。 Pairs of insulated gate field effect transistors (abbreviated as MISFETs) with extremely small threshold voltage differences are widely required for input circuits of differential amplifiers. The threshold voltage V th of the MISFET is given by V th = φ MS −(Q SS /C p )±(Q B /C p ) +2φ F. Here, φ MS : Difference between substrate material, electrode material, and work function Q SS : Surface state density Q B : Charge density of substrate (sign depends on conduction type) φ F : Fermi function C O : Capacitance due to the insulating film on the channel region. In the above equation, φ MS and φ F are uniquely determined by the substrate material and electrode material, and the factors that cause a difference in the threshold voltage of a pair of MISFETs configured on the same substrate are Q SS and It becomes Q B. That is, even if the substrate is the same, these values will differ depending on its position or due to unbalanced shape. Therefore, in order to avoid the influence of these unbalance causes, four unit MISFETs are formed on one board, and two MISFETs of the first group are configured in parallel, and the remaining MISFETs are connected in parallel. 2
A method is used in which MISFETs are used as a pair with two MISFETs in a group arranged in parallel.
第１図はこのようにして構成したMISFET対
の従来例を示す平面配置図、第２図はその−
線での断面図である。図において、１はｐ形基
板、２はその上に形成されたｎ形エピタキシヤル
成長層、３はｐ形ソース拡散層、４はｐ形ドレイ
ン拡散層、５は絶縁膜、６はソース拡散層３とド
レイン拡散層４の表面に亘つて形成されたゲート
絶縁膜、７はドレイン電極、８はソース電極、９
はゲート電極、１０はチヤネル領域である。図示
のように、ドレイン電極７を共通にした４個の単
位MISFETQ1，Q2，Q3およびQ4が形成され、単
位MISFETQ1とQ4とはソース電極８が導電体１
１を介して接続され、ゲート電極９は導電体１２
を介して接続されて、完全に並列接続された第１
の複合MISFETを形成している。一方、単位
MISFETQ2とQ3とはソース電極８およびゲート
電極９がそれぞれ導電体１３および１４を介して
接続されて、完全に並列接続された第２の複合
MISFETを形成している。このように第１の複
合MISFETと第２の複合MISFETとを対にして
用い、チヤネル領域１０は基板上に点対線に配置
されており、各単位MISFETQ1〜Q4をたすきが
けに接続することによつて各チヤネル領域相互間
の表面準位密度ＱSSおよび基板の電荷密度ＱBの
位置的な差異を補償させることを意図している。 Figure 1 is a plan layout showing a conventional example of a MISFET pair configured in this way, and Figure 2 is a diagram showing its -
FIG. In the figure, 1 is a p-type substrate, 2 is an n-type epitaxial growth layer formed thereon, 3 is a p-type source diffusion layer, 4 is a p-type drain diffusion layer, 5 is an insulating film, and 6 is a source diffusion layer. 3 and a gate insulating film formed over the surface of the drain diffusion layer 4, 7 a drain electrode, 8 a source electrode, 9
is a gate electrode, and 10 is a channel region. As shown in the figure, four units MISFETQ 1 , Q 2 , Q 3 and Q 4 are formed with a common drain electrode 7, and the units MISFET Q 1 and Q 4 have a source electrode 8 connected to a conductor 1.
1, and the gate electrode 9 is connected to the conductor 12.
the first fully parallel connected
A composite MISFET is formed. On the other hand, the unit
MISFETQ 2 and Q 3 are second composites in which the source electrode 8 and gate electrode 9 are connected via conductors 13 and 14, respectively, and are completely connected in parallel.
It forms a MISFET. In this way, the first composite MISFET and the second composite MISFET are used as a pair, and the channel regions 10 are arranged in a pair of points on the board, and each unit MISFET Q 1 to Q 4 is connected crosswise. This is intended to compensate for positional differences in surface state density Q SS and substrate charge density Q B between each channel region.
しかしながら、この従来の構成では、素子配置
の自由度が少ないという欠点があり、更に、ゲー
ト電極９以外のチヤネル領域１０に近い導電体の
配置状態の影響が大きく、第１図の従来例では、
単位MISFETQ1およびQ4からなる第１の複合
MISFETのしきい値電圧が、単位MISFETQ2お
よびQ4からなる第２の複合MISFETのしきい値
電圧よりも高くなることが確認された。 However, this conventional configuration has the disadvantage that there is little freedom in element arrangement, and furthermore, the arrangement of conductors near the channel region 10 other than the gate electrode 9 has a large influence, and in the conventional example shown in FIG.
The first complex consisting of units MISFETQ 1 and Q 4
It was confirmed that the threshold voltage of the MISFET was higher than that of the second composite MISFET consisting of the units MISFETQ 2 and Q 4 .
これは、ゲート電極９の材料および構成は勿論
のこと、チヤネル領域１０近傍の導電体、第１図
では導電体１１および１２が当該チヤネル領域１
０の表面準位密度ＱSSに影響を与えるためであ
る。 This depends not only on the material and structure of the gate electrode 9 but also on the conductors near the channel region 10, in FIG.
This is because it affects the surface state density Q SS of 0.
この発明はこのような事実にもとづいて、従来
の装置の欠点を除去し、しきい値電圧差の極めて
小さいMISFET対を得ることを目的としてい
る。 Based on these facts, the present invention aims to eliminate the drawbacks of conventional devices and to obtain a MISFET pair with an extremely small difference in threshold voltage.
第３図はこの発明の一実施例を示す平面配置図
で、この実施例は第１図の従来例に対応して構成
したもので、従来例と同一部分は同一符号で示
し、その説明を省略する。従来例では前述のよう
に点対称配置を採用していたが、この点は特性の
平衡の上で余り重要ではないのでこの実施例では
点対称にとらわれていない。そして、この実施例
においては導電体１２を延長して単位
MISFETQ1のチヤネル領域１０に近接して導電
体１２ａを設け、導電体１２の単位MISFETQ3
に及ぼす影響と同等の影響を与えるようにしてあ
る。また、導電体１１を延長して導電体１１ａ，
１１ｂを設け、この導電体の単位MISFETQ2お
よびQ4へ及ぼす影響を等しくなるようにしてい
る。このようにすることによつて複合MISFET
対のしきい値電圧の不整合は大幅に改善される。
そして、上述の配慮は各単位MISFETのチヤネ
ル領域の外縁から50μｍ以内の導電体に対してな
されるべきものである。 FIG. 3 is a plan layout diagram showing an embodiment of the present invention. This embodiment is constructed in correspondence with the conventional example shown in FIG. Omitted. In the conventional example, a point-symmetrical arrangement was adopted as described above, but since this point is not very important in terms of balancing the characteristics, this embodiment is not limited to point-symmetrical arrangement. In this embodiment, the conductor 12 is extended to form a unit
A conductor 12a is provided close to the channel region 10 of MISFETQ 1 , and the unit of conductor 12 is MISFETQ 3.
It is designed to have the same effect as the effect on In addition, the conductor 11 is extended and the conductor 11a,
11b is provided to equalize the influence of this conductor on the units MISFETQ 2 and Q 4 . Composite MISFET by doing this way
The pairwise threshold voltage mismatch is significantly improved.
The above consideration should be given to the conductor within 50 μm from the outer edge of the channel region of each unit MISFET.
第４図はこの発明の効果を示すための図で、第
４図Ａは従来構造のMISFET対のしきい値電圧
差の分布図、第４図Ｂはこの発明の構造の
MISFET対のしきい値電圧差の分布図で、縦軸
はしきい値電圧差（ｍＶ）、横軸は各電圧差領域
の分布（％）を示す。図示のようにこの発明の構
造にすることによつて、しきい値電圧差の分布は
大幅に改善される。 FIG. 4 is a diagram showing the effect of the present invention. FIG. 4A is a distribution diagram of the threshold voltage difference between a pair of MISFETs with a conventional structure, and FIG. 4B is a distribution diagram of the threshold voltage difference of a MISFET pair with a conventional structure.
This is a distribution diagram of the threshold voltage difference between a pair of MISFETs, where the vertical axis shows the threshold voltage difference (mV), and the horizontal axis shows the distribution (%) of each voltage difference region. By adopting the structure of the present invention as shown in the figure, the distribution of threshold voltage differences is greatly improved.
以上詳述したように、この発明では、同一半導
体基板内に形成された４個のMISFETのうち第
１群の２個の単位MISFETを並列に接続して構
成した第１の複合MISFETと第２群の２個の単
位MISFETを並列に接続して構成した第２の複
合MISFETとを対としたものにおいて、上記両
複合MISFETの少くとも互いに対応する単位
MISFETのゲート電極の材料および形状を等し
くするとともに、上記第１の複合MISFETの一
方の単位MISFETのチヤネル領域の外縁から５
０μｍ以内を所定形状で通る上記接続用導電体が
上記第２の複合MISFETの対応する単位
MISFETのゲート領域に対して上記所定形態と
実質的に等しい形態で通るようにしたので、両複
合MISFETはすべての面で平衡し、しきい値電
圧差の少いMISFETが得られる。 As detailed above, in the present invention, a first composite MISFET and a second compound MISFET are configured by connecting in parallel two unit MISFETs of the first group among four MISFETs formed in the same semiconductor substrate. In a pair with a second composite MISFET configured by connecting two unit MISFETs of the group in parallel, at least the units of both composite MISFETs that correspond to each other.
In addition to making the materials and shapes of the gate electrodes of the MISFETs the same, the
The connection conductor passing within 0 μm in a predetermined shape is the corresponding unit of the second composite MISFET.
Since the gate region of the MISFET is made to pass in a shape substantially equal to the above-described predetermined shape, both composite MISFETs are balanced on all sides, and a MISFET with a small difference in threshold voltage can be obtained.
第１図は従来のMISFET対の一例を示す平面
配置図、第２図はその−線での断面図、第３
図はこの発明の一実施例を示す平面配置図、第４
図はこの発明の効果を示す図で第４図Ａは従来構
造のMISFETしきい値電圧差の分布図、第４図
Ｂはこの発明の構造のMISFET対のしきい値電
圧差の分布図である。
図において、１はｐ形基板、２はｎ形エピタキ
シヤル成長層、３はｐ形ソース拡散層、４はｐ形
ドレイン拡散層、５は絶縁膜、６はゲート絶縁
膜、７はドレイン電極、８はソース電極、９はゲ
ート電極、１０はチヤネル領域、１１，１２，１
３，１４，１１ａ，１１ｂ、および１２ａは接続
用導電体、Q1，Q2，Q3、およびQ4は単位
MISFETである。なお、図中同一符号は同一ま
たは相当部分を示す。
Fig. 1 is a plan layout showing an example of a conventional MISFET pair, Fig. 2 is a cross-sectional view taken along the - line, and Fig. 3 is a plan view showing an example of a conventional MISFET pair.
The figure is a plan layout diagram showing one embodiment of the present invention.
The figures show the effects of the present invention. Figure 4A is a distribution diagram of the threshold voltage difference between MISFETs with a conventional structure, and Figure 4B is a distribution diagram of the threshold voltage difference between a pair of MISFETs with the structure of the present invention. be. In the figure, 1 is a p-type substrate, 2 is an n-type epitaxial growth layer, 3 is a p-type source diffusion layer, 4 is a p-type drain diffusion layer, 5 is an insulating film, 6 is a gate insulating film, 7 is a drain electrode, 8 is a source electrode, 9 is a gate electrode, 10 is a channel region, 11, 12, 1
3, 14, 11a, 11b, and 12a are connecting conductors, Q 1 , Q 2 , Q 3 , and Q 4 are units
It is MISFET. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
縁ゲート電界効果トランジスタ（以下、絶縁ゲー
ト電界効果トランジスタをMISFETと略称す
る。）のうち第１群の２個の単位MISFETを並列
に接続して構成した第１の複合MISFETと第２
群の２個の単位MISFETを並列に接続して構成
した第２の複合MISFETとを対としたものにお
いて、上記両複合MISFETの少なくとも互いに
対応する単位MISFETのゲート電極の材料およ
び形状を等しくするとともに、上記第１の複合
MISFETの一方の単位MISFETのチヤネル領域
の外縁から50μｍ以内を所定形態で通る上記接続
用導電体が上記第２の複合MISFETの対応する
単位MISFETのゲート領域に対して上記所定形
態と実質的に等しい形態で通るようにしたことを
特徴とする絶縁ゲート電界効果トランジスタ対。1 Out of four unit insulated gate field effect transistors (hereinafter, insulated gate field effect transistors are abbreviated as MISFETs) formed in the same semiconductor substrate, two unit MISFETs of the first group are connected in parallel. The configured first composite MISFET and the second
In a pair of a second composite MISFET formed by connecting two unit MISFETs of the group in parallel, the materials and shapes of the gate electrodes of at least the mutually corresponding unit MISFETs of both composite MISFETs are made equal to each other, and , the first composite above
The connecting conductor passing in a predetermined form within 50 μm from the outer edge of the channel region of one unit MISFET of the MISFET is substantially equal to the predetermined form with respect to the gate region of the corresponding unit MISFET of the second composite MISFET. 1. A pair of insulated gate field effect transistors, characterized in that the transistors have a conductive shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9078679A JPS5615079A (en) | 1979-07-16 | 1979-07-16 | Insulated gate field effect transistor couple |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9078679A JPS5615079A (en) | 1979-07-16 | 1979-07-16 | Insulated gate field effect transistor couple |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5615079A JPS5615079A (en) | 1981-02-13 |
| JPS6148793B2 true JPS6148793B2 (en) | 1986-10-25 |
Family
ID=14008272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9078679A Granted JPS5615079A (en) | 1979-07-16 | 1979-07-16 | Insulated gate field effect transistor couple |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5615079A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2154820B (en) * | 1984-01-23 | 1988-05-25 | Int Rectifier Corp | Photovoltaic relay |
| JPH0642537B2 (en) * | 1985-11-15 | 1994-06-01 | 株式会社東芝 | Semiconductor device |
| DE3818533C2 (en) * | 1987-06-01 | 1994-05-26 | Mitsubishi Electric Corp | Field effect transistor |
| JP2597749B2 (en) * | 1990-11-19 | 1997-04-09 | 三菱電機株式会社 | Peak hold circuit |
-
1979
- 1979-07-16 JP JP9078679A patent/JPS5615079A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5615079A (en) | 1981-02-13 |
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