JP3421566B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a MOS type transistor, and more particularly, to provide a structure of a transistor in which an isolation diffusion layer can be omitted and surface leakage current is extremely small.

[0002]

2. Description of the Related Art In recent years, the integration density of elements in a semiconductor integrated circuit has been increasing, and therefore the progress of miniaturization technology has been remarkable. However, so-called SSI (Small Scale Integration)
In the area of (2), the actual situation is to increase the degree of integration by combining conventional technologies in various senses. As mentioned above, in fields where there is little or no financial obstacle even if the degree of integration is low, such as SSI, the concept of the latest technology area is used, but the equipment that realizes the latest technology cannot be invested. There are many cases.

In a semiconductor integrated circuit, it is natural that the size of each electric element is made as small as possible, but depending on how it is considered to be electrically separated, an unnecessary separation diffusion layer may be formed. The relatively large area and the large area of the wiring circuit including the gate electrode and the lead-out pad of the electrode terminal in the peripheral portion substantially hinder the improvement of the degree of integration. Among these problems, the reduction of the separation diffusion layer is planar, and thus a large rationalization is not recognized. In other words, a rationalization method by separating the substrate from above and below to prevent lateral expansion or a method of eliminating the separation layer at all, or an alternative method can be considered. Also, the other wiring circuit needs a minimum width, so we will try to solve it by a three-dimensional layout, and proceed in the direction of two or more layers of wiring. I've been

A typical conventional pattern will be described with reference to the plan view shown in FIG. An N-type growth layer epitaxially grown on a semiconductor substrate is separated and formed into a desired shape by a separation layer 21 formed of a P-type diffusion layer to provide N-type islands 22 and 23. The epitaxially grown N type islands 22 and 23 surrounded by the isolation layer 21 are used as MOS type transistor regions, and the first and second source regions 2 are separated from each other.
4, 25 and first and second drain regions 26, 27 are formed. First and second source electrodes 28 and 29, first and second drain electrodes 30 and 31, and first and second gate electrodes 32 and 33 are provided through thin oxide films from respective regions constituting the MOS transistor. . Separation layer 21 as shown
Separates two MOS type FETs like writing the letter "day". Here, a part of the separation layer separating the two is on a straight line other than the peripheral separation layer (the shape of the "mouth" in FIG. 4) in order to insulate the two FETs from other circuit elements. As a matter of course, the separation layer may be replaced by an inversion prevention layer that is usually provided in a MOS type FET.

Considering the concrete numerical values, the width of the separation layer 21 is about 15 μm when completed when the thickness of the epitaxial layer is 5 μm and the width on the pattern of the separation layer is 5 μm. is there. That is, two FEs with a width of 30 μm
Will separate T. On the other hand, if the inversion prevention layer is used for separation in the middle, a pattern of 5 μm under the same conditions is about 10 μm at the time of completion.
Can be separated.

Although this alone has the effect of downsizing, the integrated circuit in which such an FET is incorporated is very small,
In most cases, the thickness of the epitaxial growth layer of 5 μm is insufficient due to the requirements of other elements. Therefore FET
Considering an example in which the epitaxial layer has a thickness of 15 μm due to the requirements of other circuit elements, the width of one separation layer exceeds 20 μm. As a result, two F at 40 μm
Separation of ET is performed, which further reduces the degree of integration.

[0007]

As described above, the spread of the separation layer having a considerable share in order to improve the integration degree of the SSI is rationalized on the premise of the special use method of the FET so that the integration degree is improved. Is to improve. The method of trying to replace the separation layer by the inversion prevention layer is also an excellent proposal, but by further advancing it, a separation layer does not exist, but it has an effect of changing to it and contributes to the realization of the integration degree. The purpose is to do.

Not only in the case of a thin epitaxial layer, but also in the isolation layer, the share of the isolation layer is further increased due to other factors. Therefore, a plurality of FETs are isolated by one isolation layer and each FET does not leak. That is, it proposes a structure that does not involve each other.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and enables a plurality of FETs to operate in one island without interfering with each other. It was done. The present invention relates to a plurality of FETs formed in one island which is substituted by one isolation layer or inversion prevention layer.
And a part of a circuit in which the operations are mutually turned on / off, and an opposite conductivity type epitaxial growth layer provided on one main surface of a one conductivity type semiconductor substrate and a one conductivity type An island region formed by a separation layer or an inversion prevention layer, two source regions and two drain regions which are formed by the self-alignment method and are separated from each other by one conductivity type in the island region, respectively, and at least a source region; Each of the gate electrodes provided on the opposite channel region of the drain region via a thin insulating film and the source electrodes arranged at least without a gap in plan view with the gate electrodes facing each other at least A source electrode that extends wider than the source region of each FET, and a drain that is disposed so as not to have at least a gap in plan view with the gate electrode. Composed of FET which in the down electrodes and a respective drain electrode Zaisa widely extended from the drain region of each of the FET that facing the at least one another.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides a rationalization of a separation method for an integrated circuit having a plurality of FETs and forming a circuit which operates by turning on / off each other. Figure 1
2 and its AA cross-sectional view of FIG. 2 will be used to explain in detail using an integrated circuit using two FETs, which is an embodiment of the present invention. An epitaxial layer 2 of another conductivity type is epitaxially grown on a semiconductor substrate 1 of one conductivity type and surrounded by a separation layer 3 to obtain an island region inside. Two FETs are formed in this island region. That is, the first and second source regions 4 and 8, the first and second source electrodes 5 and 9, the first and second drain regions 6 and 10, and the first and second drain electrodes 7 and 11, First and second gate electrodes 12 and 13 are provided.

Each region and electrode are formed by a conventional method, and the gate electrode and each region are formed by a self-alignment method, and a thin gate oxide film 14, a thick insulating film to be used for an interlayer insulating film and a field oxide film. 15. Although not shown, it is inevitable that a protective insulating film or the like is provided. One of the features to be noted in the present invention is that there is no isolation layer separating the two FETs. Further, the first and second source electrodes 5 and 9 in the semiconductor device according to the present invention have two characteristics. The first point is that the opposite sides extend broadly from at least the respective source regions 4, 8. To further explain that it extends widely, as shown in FIG. 1, the upper side of each of the first and second source regions 4 and 8 is sufficiently covered, and yet the sides which oppose each other are covered. That is, the arrangement is protruding.

The second point is that there is no gap between the first and second source electrodes 5 and 9 and the first and second gate electrodes 12 and 13 in plan view as shown in FIG. As shown in FIG. 2, the cross-section has a distance of only the thick insulating film 15 of the interlayer insulating film. This is a so-called “flush” that is not separated in a plane, but it is a matter of course that they are separated in the sense of being electrically separated in a cross section. As a matter of course, they are separated from each other unless there is a special condition that the source electrode and the gate electrode are always kept at the same potential. Similarly, the first and second drain electrodes 7 and 11 are also 2
It has two characteristics. As described above, the first point is that the sides facing each other are at least the drain regions 6 and 1 respectively.
It extends widely from zero. The second point is the first,
Second drain electrodes 7 and 11 and first and second gate electrodes 1
That is, there is no gap between 2 and 13. In this case as well, the meaning of extending and having no gap is used in the same meaning. According to the present invention, as can be understood from FIGS. 1 and 2, a separation layer 3 for separating two FETs from other circuit elements is provided.
There is no isolation layer that separates the two FETs from each other. In explaining why the present invention does not positively require separation, the FET having "first" attached to each region and each electrode described above is referred to as a first FET, and the FET having "second" attached is referred to as a second FET. Defined as 2 FET. The present invention is based on the premise that the two FETs are the same type of FET in which the two FETs are constantly turned on and off, so if one FET is ON, the other is O.
It is FF. For example, in FIG. 1, the first FET is ON.
If so, the second FET is OFF. The voltage is applied to each electrode and region as follows. That is, the first gate electrode 12 and the second gate electrode 13 are at high level and low level potentials respectively, and the first drain region 6 and the second drain region 10 are at low level potentials via the electrodes 7 and 11, respectively. The potential and the high level potential are set. Here, in the N-channel FET, since a reverse bias is applied to the drain region, a depletion layer is formed from the second drain region 10 and extends to the first drain region 6. At this time, the ionic polarization of undesired impurities from the sealing resin such as epoxy resin that generally seals the semiconductor device affects the gate oxide film 14 and the thick insulating film 15. If it does not extend widely to the electrodes facing each other, the influence of the above-mentioned ionic polarization easily occurs between the drain regions 6 and 10, and it is easy to invert, and the inversion layer is formed from the second drain region 10.
It reaches the first drain region 6 and acts as a leak between both drains. Second when the leak is off
It is natural that the FET is not convenient. Here, in the FET having the structure of the present invention, a low voltage is applied to the drain of the first FET that is ON. Specifically, since it is at the ground level, there is a possibility that inversion can be prevented.
That is, it is difficult to reverse. If the electrode is made wider and wider than the drain region, the same effect as if the inversion layer did not occur is produced. Next, when the first FET is OFF and the second FET is ON, a completely opposite phenomenon occurs and the influence of the inversion layer can be ignored. Therefore, it is important to design the two facing sides to be wider than the drain region. Further, in the present invention, as described above, the interaction of the two FETs incorporated in one island is eliminated, and the separation layer is omitted. Therefore, as a condition, the ON / OFF operations are mutually performed. It is an indispensable requirement to have a circuit configuration. Further, if one FET is an N-channel type because it is on the same island, other FETs need to be N-channel FETs.

Next, another embodiment of the present invention will be described with reference to FIG. Here, in order to avoid duplication, the same things as those described with reference to FIGS. 1 and 2 are omitted, and only different portions will be described. In this embodiment, the sides of the source electrode and the drain electrode which face each other are naturally extended, and the opposite sides of the source and drain electrodes extend wider than the respective source and drain regions. Further, in the above-mentioned embodiment, the gate electrodes are arranged so as not to have a gap in plan view, but in this embodiment, the overlapping portions 16, 17, 1 in plan view with respect to the gate electrodes are arranged.
8 and 19, they are electrically separated in a cross section, in other words, electrically by the interlayer insulating film.

In a further developed embodiment, the overlapping portions 16 and 17 are provided only in the drain region, and the source region is arranged so as not to have a gap with the gate electrode as described in the first embodiment. Is also effective. This is because in the case of an N-channel FET, the depletion layer generated in the drain is a problem, and it is difficult to generate it in the source region, and even if it occurs, it has little effect, so both electrodes are on a thin gate electrode. , And only the drain may be overlapped. Furthermore,
This is because by arranging the source and drain electrodes or one of the electrodes, particularly the drain electrode, extending over the gate electrode, it is possible to completely prevent leakage even if the mask is misaligned.

[0015]

According to the present invention, it has been shown that a separation layer for separating a plurality of FETs is not necessary in a circuit configuration in which a plurality of FETs are turned on / off in pairs. . In an integrated circuit with a small number of elements such as SSI, omitting or rationalizing the separation layer is the first shortcut to improve the degree of integration. It has been found that the planar area newly required by the present invention serves as a sufficient separation by widening the conventional source and drain electrodes by about 2 μm to 6 μm. On the other hand, the rationalized area is about 15 μm to 40 μm as described above. Therefore,
Only the difference between these values improves the degree of integration.

[Brief description of drawings]

FIG. 1 is a schematic plan view for explaining an embodiment of the present invention.

FIG. 2 is a schematic sectional view for explaining an embodiment of the present invention.

FIG. 3 is a schematic plan view for explaining another embodiment of the present invention.

FIG. 4 is a schematic plan view for explaining a conventional example.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-61-144842 (JP, A) JP-A-59-198764 (JP, A) JP-A-56-100442 (JP, A) JP-A-3- 290950 (JP, A) JP-A-6-275803 (JP, A) JP-A-3-153070 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8234 H01L 27 / 088

Claims (3)

(57) [Claims] 1. In an integrated circuit, which comprises a plurality of FETs formed on one island, the operations of which are mutually ON / OFF operations, one main component of a semiconductor substrate of one conductivity type A reverse-conductivity type epitaxial growth layer provided on the surface, an island region formed by a one-conductivity type separation layer, and at least each independent island formed by the self-alignment method with one conductivity type separated in the island region. Two source regions, at least two drain regions, each gate electrode provided on at least the channel region facing the source region and the drain region via a thin insulating film, and at least a gap between the gate electrodes in plan view. The source electrodes disposed without the gate electrodes, and at least the sides of the source electrodes extending in a direction opposite to each other are wider than the source regions, and the gate electrodes. And a drain electrode which is arranged without a gap in plan view, and each side of the drain electrodes extending in a direction at least facing each other is wider than the drain region. 2. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode extend wider on both sides than the respective electrically extracted regions. 3. The semiconductor device according to claim 1, wherein one or both of each source electrode and each drain electrode extend onto a gate region formed by each of them.