JPS6148187B2 - - Google Patents

Info

Publication number
JPS6148187B2
JPS6148187B2 JP56099270A JP9927081A JPS6148187B2 JP S6148187 B2 JPS6148187 B2 JP S6148187B2 JP 56099270 A JP56099270 A JP 56099270A JP 9927081 A JP9927081 A JP 9927081A JP S6148187 B2 JPS6148187 B2 JP S6148187B2
Authority
JP
Japan
Prior art keywords
terminal
management data
processing
polling
terminal device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56099270A
Other languages
English (en)
Japanese (ja)
Other versions
JPS581234A (ja
Inventor
Noboru Yamamoto
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56099270A priority Critical patent/JPS581234A/ja
Publication of JPS581234A publication Critical patent/JPS581234A/ja
Publication of JPS6148187B2 publication Critical patent/JPS6148187B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Debugging And Monitoring (AREA)
JP56099270A 1981-06-26 1981-06-26 端末制御方式 Granted JPS581234A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56099270A JPS581234A (ja) 1981-06-26 1981-06-26 端末制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56099270A JPS581234A (ja) 1981-06-26 1981-06-26 端末制御方式

Publications (2)

Publication Number Publication Date
JPS581234A JPS581234A (ja) 1983-01-06
JPS6148187B2 true JPS6148187B2 (enrdf_load_html_response) 1986-10-23

Family

ID=14242987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56099270A Granted JPS581234A (ja) 1981-06-26 1981-06-26 端末制御方式

Country Status (1)

Country Link
JP (1) JPS581234A (enrdf_load_html_response)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5393739A (en) * 1977-01-27 1978-08-17 Mitsubishi Electric Corp Connecting system for peripheral equipment

Also Published As

Publication number Publication date
JPS581234A (ja) 1983-01-06

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