GB2176917A

GB2176917A - Data port

Info

Publication number: GB2176917A
Application number: GB08515517A
Authority: GB
Inventors: Martin Sproat
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1985-06-19
Filing date: 1985-06-19
Publication date: 1987-01-07
Also published as: GB2176917B; GB8515517D0

Abstract

In a packet system a data port between a data terminal and a controlling processor uses a USART (Universal Synchronous/Asynchronous Receiver/transmitter), which in conventional practice is used as a byte-by-byte interface, with each byte to the transferred causing a separate interrupt. On a busy line or where several ports are controlled from one processor this causes many processor interrupts. To minimise this, the data incoming to the port is monitored in the port to detect preset byte combinations (e.g. message end), the presence of such a combination causing an interrupt. Bytes on reception go into a buffer, which is monitored to see how full it is. When it reaches a preset level of fullness an interrupt is also sent. In both these cases the interrupt causes data transfer to the processor. In addition the port has a buffer for the reception of data output from the processor; this is monitored and if empty the port issues an interrupt to "tell" the processor that it can receive data. These arrangements provide a significant reduction in the number of interrupts needed, which is important, especially where the processor serves a number of data ports. <IMAGE>

Description

SPECIFICATION Data port The present invention relates to data ports, especially for use as the terminals of a packet switching system.

An example of a conventional terminal device with a tabulation of its functions is shown in Figure 1. Here an universal synchronous asynchronous Receiver-Transmitter device (USART) presents an interrupt-per-character type of interface to the controlling microprocessor. Thus the microprocessor has to stop its current task and change to a different program to retrieve/send a data byte to the terminal device and this switching of tasks is known as context switching. With low traffic or a small number of serial terminals connected to a microprocessor, the additional overhead of performing a context switch to handle the interrupt due to the transmission or reception of a data byte is not significant. However, where a higher message rate (or a larger terminal population) is serviced there are gains in reducing the number of times the microprocessor has to perform the context switch.In these cases the time not expended in handling unnecessary interrupts can be used to increase the effective message handling capacity of the microprocessor.

An object of the invention is to provide a data port arrangement in which the number of interrupts is reduced as compared with the prior art device referred to above.

According to the invention, there is provided a data port via which data is to be transferred between an input and a processor, which includes buffer means into which data bytes are inserted on reception via the input, first monitoring means to monitor the bytes as they are received and inserted into the buffer means in search of a preset byte or byte combination, or one of a plurality of preset bytes or byte combinations, means responsive to the detection by said monitoring means of a said preset byte or byte combination to send an interrupt signal to the processor so that the latter can interrupt its current operation to deal with the transfer of the data in said buffer means to the processor, and second monitoring means for monitoring the number of bytes in said buffer means to detect when the number of bytes in said buffer means reaches a preset number to send an interrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the data in said buffer means to the processor.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which; Figure 2 shows in simplified form a data port embodying the invention.

Figure 3 tabulates the data processing operations for a data port such as that of Figure 2, with reference to asynchronous full duplex operation.

Figure 4 is a more detailed representation of a realisation of a data port embodying the invention.

A major application area for data ports embodying the invention is that of serial terminal interface devices in the packet switching area where information is naturally acquired in significant blocks of characters. The approach is, however, flexible enough to be applied to any serial data link with known terminating characters.

The Packet Access Port, (Figure 2) is a special case of a USART interface device where the "housekeeping" operations of the interface are hidden away from the host microprocessor. Conceptually the data interface is one in which the microprocessor sends or receives a string of data characters as if to an individual memory location. The Packet Port then transmits the data to the serial terminal or awaits the next byte from the serial terminal (if the Packet Port is in receive mode). The serial terminal itself, and the connections between it and the USART, are not shown in Figures 2 and 4.

We now consider the basis of the mechanism which reduces the effective interrupt rate for received data. On the receiving interface, bytes are received from the terminal and transferred into a buffer, the Rx Buffer. At this point the contents of the data byte are inspected by logic in the USART.

If the received character is one of a defined set of characters (expected as a terminating character) then the packet port raises a processor interrupt if (and only if) the byte was received without error.

The set of characters is part hard wired into the device, and a number of the set of characters is under the control of the local microprocessor. The microprocessor programmed characters are set up by the micro writing the characters in registers contained in the Packet Port and forming part of the USART.

Other than the detection of valid terminating characters there are two cases where processor interrupts may be made by the Packet Port: 1) The Packet Port raises an interrupt when the Rx Buffer in the Packet Port is within a limited number of bytes of being full. This interrupt alerts the microprocessor that the Rx Buffer needs to be emptied.Normally the data would be copied into a buffer store elsewhere in the microprocessor system.

2) The Packet Port raises an interrupt when a byte has been received incorrectly at the serial input, and in this case the microprocessor intervention is necessary to clear the fault and reset the USART function.

With certain versions of Packet Assembler Disassembler Packet switches, it may be necessary to raise interrupts only on the basis of the last two received characters, such as the IA5 character sequence DLE ETX used as a terminating character sequence, and this facility also exists in the Port.

IA5 is an international standard for "instructiontype" characters used in packet systems. A number of two-character sequences are supported, some particular (such as DLE ETX mentioned earlier) and some under microprocessor control, i.e. the processor can set registers in the Packet Port to contain particular character sequences which when seen in the received ata stream cause the micro to be interrupted by the Packet Port.

The mechanism that reduces the effective inter rupt rate for transmitted data, i.e. data to be sent from the microprocessor via the packet port to the terminal, is now discussed. Normally a byte would be transferred by the micro to the USART and when that byte was sent and the USART was next available it would interrupt the micro to trigger it to send further data. The Packet Port uses the same interrupts but for a block of data rather than one byte. The Packet Port contains a buffer, Tx Buffer, which can accommodate more than 30 bytes, and a counter which keeps track of the num ber of bytes currently in the buffer. If the buffer is empty then the Packet Port raises an interrupt to the micro to request more data.It is possible for the microprocessor to poll the Packet Port and see if there is further space for data and if so to add more. The reduction in interrupts is related to the amount of buffer space in the Packet Port.

In the above cases the microprocessor finds out the reason for the interrupt by interrogating regis ters in the Packet Port, i.e. in the block Status and Control Register.

The amount of processor interrupt reduction gained with this approach depends on the length of the buffer in the Port. Ideally this should be as long as the longest packet to be sent but in hard ware terms this may not be financially attractive as the additional memory may not be frequently used and may consume a large amount of die space on a chip. In practice 30-60 bytes of buffer storage provides useful reduction in the processor activity for a packet transfer.

This reduces the number of interrupts due to the receiving side by at least a factor of four, as most console command inputs consist of at least txo characters and a carriage return character, and usually more. A beneficial size of receiving buffer would be approximately 45 characters, as this is more than one lineful of teletext input.

The effect on the transmission side is directly re lated to the length of the buffer. As many applica tions programs tend to output whole lines of data, i.e. 30-80 characters at a time, the reduction in the numbers of interrupts is directly related to this buffer length within the device and the interrupt rate reduction is in the region of a factor of 30-80.

The interface hidden from the microprocessor is the interface containing the serial device, USART, section of the Packet Port, (Figure 2). This is effec tively an internal interface, as indicated in Figure 2, within the Packet Port but is defined here as it may make the realisation of such a device simpler. The operation of the internal interface is shown in tab ular form in Figure 3. Hence no detailed textual de scription of this is given.

The USART function is conventionally performed on a byte-by-byte basis raising interrupts when a byte is received. Information relating to that trans fer of bits of information, such as whether the byte was received correctly or not, are stored within the USART. The Packet Port internal interface, specifi cally the interrupt handling logic function block of Figure 2, on detection of the interrupting condition from the receiving serial function, checks the status of the USART function and confirms whether the byte was received successfully or not.

At this point one of the following two actions occurs: 1) If the byte was unsuccessfully received then the microprocessor is interrupted to clear the fault.

2) If the byte was received successfully then the Packet Port retrieves the byte from the USART function and prepares the USART to receive the next byte.

This action of recovering a byte of data has added a further byte to the length of the data in the data buffer. The Packet Port updates the count of the number of bytes it has in its internal buffer.

The microprocessor can interrogate this counter in the Packet Port at any time to find out how many bytes to transfer out of the buffer when data is to be transferred.

In the transmit direction the USART transmission function is controlled by the rest of the Packet Port.

If data is held in the buffer in the Packet Port (loaded by the microprocessor) then the logic in the Packet Port passes bytes to the USART function whenever the USART function signals that it is ready to receive a data byte. Thus the transmission of data back to the terminal is always achieved in the shortest possible time.

Whenever the transit buffer in the Packet Port is empty no bytes are transferred. Whenever the USART function signals that it is ready to receive a byte and the transmit buffer is empty, then the interrupt handling logic causes an interrupt to the host micro.

One action interrupts this flow of data across the link and this is the request by the microprocessor to access the status ports of the USART function.

Under these access conditions the transfer of data between the Packet Port buffer and the USART function will cease and the data highways used between the USART function and the rest of the Packet Port will be diverted and will be made to appear as if directly connected to the host microprocessor. The microprocessor will be deemed to have released the Packet Port when the address lines no longer select it. Internal data transfers, if there are any remaining, will then recommence.

As stated previously the Status ports of the USART function shall be made available to the microprocessor. This occurs from the Status and Control Register, via the Databus. The interface appears to the microprocessor as a number of memory locations which may be situated in memory or in the I/O space of the microprocessor concerned.

In addition to the status ports the microprocessor also has access to a number of other registers within the Packet Port to program which character sequences raise interrupts on the host microprocessor. Other functions using these registers are things like baud rate generation (including 1200/75 baud) for asynchronous terminals. These registers are protected against inadvertent re-programming using the following method: 1) Each register has a bit associated with it in a separate register called a control register.

2) The contents of a register can be changed only if the corresponding bit (and only that bit) in the control register has been set to a logical true state.

3) If the bit in the control register is set and a write operation is attempted on the register it succeeds.

4) If the bit is not set then the byte sent by the microprocessor is ignored and a flag is set in the status register so that the microprocessor can check and know that the write operation has failed.

5) On powering up, all the internal registers other than those of the USART function have the matching enabling bits in the control register reset to a logical false state i.e. are effectively "write protected".

A further function of which the Packet Port is capable is that of performing automatic echoing of characters received. This function is enabled by setting a bit in the control register. The function, when in operation, causes any characters received from the terminal USART function to be copied into the transmitting buffer at the same time as being written into the receiving buffer. During such operation the absence of date blocks in the transmitting buffer should not cause any interrupts.

Hence the monitoring of that buffer is disabled, or the results of such monitoring ignored. The function can be active whether the transmission mode is full or half duplex, and the buffering adequately copes with the load.

The Packet Port serial interface supports full or half duplex operation. The Packet Port device has a bit in the control register structure which identifies whether the method of transmission is half or full duplex. The Default state is half Duplex, and it is possible for the Packet Port to detect the presence of full duplex and ignore this bit setting and operate full duplex. The converse is not true. If the bit is set to full duplex and the distant terminal is expecting half duplex then errors may occur by the Packet Port sending data to the terminal when it is not ready for it.

The Packet Port device contains a programmable baud rate generator which needs an external clock.

It provides Transmit and Receive clocks at the baud rates currently envisaged for PSS (including the mixed mode 1200/75 that very few USART devices currently on the market support internally) by dividing down from a reference clock provided at the input to the Packet Port device.

The description given above is of a single device performing the function of an integral packet switching type of serial terminal. One of the forms of realising this function is shown in Figure 4. It consists of two basic devices a USART and a custom chip called a Packet Shell Device. It will be seen that the Packet Shell Device embodies all of the port except the USART. This device provides all the USART interfacing and data buffering described above.

Claims

1. A data port via which data is to be transferred between an input and a processor, which includes buffer means into which data bytes are inserted on reception via the input, first monitoring means to monitor the bytes as they are received and inserted into the buffer means in search of a preset byte or byte combination, or one of a plural- ity of preset bytes or byte combinations, means responsive to the detection by said monitoring means of a said preset byte or byte combination to send an interrupt signal to the processor so that the latter can interrupt its current operation to deal with the transfer of the data in said buffer means to the processor, and second monitoring means for monitoring the number of bytes in said buffer means to detect when the number of bytes in said buffer means reaches a preset number to send an interrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the data in said buffer means to the processor.

2. A packet data port via which packetized data is to be transferred between a data terminal and a processor, which includes bumer means into which the data bytes and the associated control and addressing bytes are inserted on reception from the terminal, first monitoring means to monitor the bytes as they are received and inserted into the buffer means in search of a preset byte or byte combination, or one of a plurality of preset bytes or byte combinations, means responsive to the detection by said monitoring means of a said preset byte or byte combination to send an interrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the packetized data and its associated control and addressing bytes in said said buffer means to the processor, and second monitoring means for monitoring the number of bytes in said buffer means to detect when the number of bytes in said buffer means reaches a preset number to send an interrrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the data in said buffer means to the processor.

3. A data port as claimed in claim 1 or 2, in which the bytes or byte combinations to be monitoted for by the first monitoring means are part hardwired into the device and part provided by software, in which a said byte or byte combination is subjected to error checking operations and only accepted as valid if found to be correct, and in which if a said byte or byte combination is found by a said error check to be incorrect an interrupt is sent to the processor so that it can interrupt its current operations and take such remedial action as is necessitated by the error.

4. A data port as claimed in claim 3, and in which some of the preset bytes or byte cornbination provided by software are written into the port from the associated processor.

5. A data port as claimed in claim 4, in which the data port includes a further buffer means for the reception of data from the processor for transmission via the input or the data terminal, in which further monitoring means monitors the contents of said further buffer means to assess how many bytes are therein, and in which if the further buffer means is found to be empty then an interrupt is sent to the processor so that it can emit data bytes to the data port, if it has any bytes to emit.

6. A data port as claimed in claim 5, and which includes means responsive to a request signal from the processor for information as to whether the data port is able to receive data bytes to initiate a said interrupt if the port can receive bytes.

7. A data port as claimed in any one of claims 1 to 6, and in which in response to a said interrupt the processor interrogates the data port to assess the cause of the interrupt, whereafter it responds in accordance with the said cause.

8. A data port as claimed in claim 5 or any claim appendent thereto, in which the data port can be used in an echo mode, wherein data characters received for passage to the processor are automatically echoed to the point of origin thereof, in which when the data port is functioning in the echo mode received characters are copied into the further buffer means in addition to being placed in the first buffer means, and in which when the data port is working in the echo mode said further monitoring means is disabled or the results of such monitoring ignored.

9. A system which includes a number of data ports each as claimed in any one of claims 1 to 8, and a processor which co-operates with all of said data ports.

10. A data port for use in a packet switching system, substantially as described with reference to Figures 2, 3 and 4 of the accompanying drawings.

New claims or amendments to claims filed on 28 January 1986.

New claims 11-13 added

11. A data port via which data is to be transferred serially between an input and a processor, which includes buffer means into which data is inserted on reception in a byte-by-byte manner via the input, first monitoring means to monitor the bytes as they are received and inserted into the buffer means in search of a preset byte or byte combination, or one of a plurality of preset bytes or byte combinations, means responsive to the detection by said monitoring means of a said preset byte or byte combination to send an interrupt signal to the processor so that the latter can interrupt its current operation to deal with the transfer of the data in said buffer means to the processor, and second monitoring means for monitoring the number of bytes in said buffer means to detect when the number of bytes in said buffer means reaches a preset number to send an interrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the data in said buffer means to the processor, the arrangement being such that a portion of a data block can be transferred from the buffer means to the processor while further data bytes are being received by the data port.

12. A packet data port via which packetized data is to be transferred serially between a data terminal and a processor, which includes buffer means into which the data bytes and the associated control and addressing bytes are inserted on reception from the terminal, which insertion is effected in a byte-by/ byte manner, first monitoring means to monitor the bytes as they are received and inserted into the buffer means in search of a preset byte or byte combination, or one of a plural- ity of preset bytes or byte combinations, means responsive to the detection by said monitoring means of a said preset byte or byte combination to send an interrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the packetized data and its associated control and addressing bytes in said said buffer means to the processor, and second monitoring means for monitoring the number of bytes in said buffer means to detect when the number of bytes in said buffer means reaches a preset number to send an interrupt signal to the processor so that the latter can interrupt its current operations to deal with the transfer of the data in said buffer means to the processor, the arrangement being such that a portion of a block of packetised data can be transferred from the buffer means to the processor while further data bytes of that block are being received by the data port.

13. A data port as claimed in claim 12, in which the data port includes a further buffer means for the reception of data from the processor for transmission via the input or the data terminal, further monitoring means which monitors the contents of said further buffer means to assess how many bytes are therein, means under control of the monitoring means whereby if the further buffer means is found to be empty then an interrupt is sent to the processor so that it can emit data bytes to the data port, if it has any bytes to emit, and means responsive to a request signal from the processor for informaiton as to whether the data port is able to receive data bytes to initiate a said interrupt if the port can receive bytes.