JPS6146073A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To set the operation of writing and the operation of reading severally independently, and optimize both operation by injecting electrons to a floating gate electrode from a control gate electrode and writing informations. CONSTITUTION:Negative voltage is applied to a well region 5 by a well-region voltage control circuit 3, and positive voltage is applied to a conductive layer 11 and semiconductor regions 13, 15 as drain regions by an X decoder 1 and a Y decoder 2. Channel currents flow through a field-effect transistor having first threshold voltage and channel currents do not flow through a field-effect transistor having second threshold voltage under the state. That is, writing operation can be conducted by unidirectional electron injection to a conductive layer 9 from the conductive layer 11 by shaping an insulating film 10, and the electric characteristics of writing operation can be set independently regardless of reading operation, thus optimizing writing operation, then improving the efficiency of writing.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device (
The present invention relates to a technology that is effective when applied to FAMOS (hereinafter referred to as FAMOS).

[Background Art] A FAMOS memory cell includes a floating gate electrode provided above a semiconductor substrate via a first gate insulating film, a control gate electrode provided above the floating gate electrode via a second gate insulating film, and a source. It is constituted by a field effect transistor consisting of a region and a drain region.

This FAMOS write operation is performed as follows.

With respect to the semiconductor substrate and the source region, a high voltage is applied to the control gate electrode and the drain region to cause a channel current to flow through the channel region of the field effect transistor having the first threshold voltage. As a result, hot carriers are generated in the high electric field region near the drain. These hot carriers are injected as information into the floating gate electrode through the first gate insulating film due to the potential relationship between the semiconductor substrate, the drain region, and the control gate electrode. Writing is performed by this hot carrier injection, and a field effect transistor having a second threshold voltage is formed.

Further, the read operation of the FAMOS is performed as follows.

For the write operation, a low voltage is applied to the control gate electrode and the drain region to cause a channel current to flow. The amount of this channel current changes depending on whether it is the first or second threshold voltage, so the information rr OI+ or 1
11 I+ is read.

And FAMOS is for speeding up.

There is a need to improve the write efficiency of write operations and the read efficiency of read operations.

Writing efficiency can be improved by increasing the voltage applied to the control gate electrode and the drain region, increasing the electric field strength near the drain region, and increasing the amount of hot carriers generated.

The read efficiency can be improved by increasing the voltage applied to the drain region and increasing the channel current.

However, since write and read operations are essentially biased in the same direction, although the applied voltage may be different in magnitude, improving write efficiency will also increase the likelihood of hot carriers being generated during read operations. Furthermore, during a read operation, hot carriers are gradually injected into the floating gate electrode, causing a fluctuation in the threshold voltage of the field effect transistor, which is a so-called erroneous write.

The present inventor has developed the results of studies on such technology.

As mentioned above, the problem has been found that since the write operation and the read operation utilize contradictory characteristics, it is extremely difficult to set each of them optimally.

Regarding the operating principle of FAMOS, please refer to the magazine "Nikkei Electronics" published by Nikkei McGraw-Hill, January 5, 1981, p. 181.

[Object of the Invention] An object of the present invention is to provide technical means that can optimally set write operations and read operations in FAMOS.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.6 In FAMOS, information is transmitted by injecting electrons from the control gate electrode to the floating gate electrode. By performing the write operation, the write operation and the read operation can be set independently, so that optimization of both can be achieved.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

[Embodiment Figure 1 is a FAMO diagram for explaining an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a memory cell array of S. FIG.

In all the examples, parts having the same functions are given the same reference numerals, and repeated explanations will be omitted.

In FIG. 1, 1 is an X decoder, and a memory cell M
The word lines WL are connected to the control gate electrodes of the word lines WL. This X decoder 1 is for applying a predetermined voltage (for example, 0 [V] or +5 [V]) to the controller 1 to the roll gate electrode of a predetermined memory cell M to perform a write operation or a read operation. It is.

Reference numeral 2 denotes a Y decoder, which is connected to a plurality of data lines DL connected to the drain region of the memory cell M. This Y decoder 2 applies a predetermined voltage (for example, +25 [V] or a floating state, or the same voltage as the well, or +5 [V]) to the drain region of a predetermined memory cell M, and performs a write operation or a read operation. It is for the purpose of

A well region voltage control circuit 3 is connected to a well region in which a plurality of memory cells are arranged. This well region voltage control circuit 3 is for controlling the voltage (for example, +25 [V] or 0 [V]) applied to the well region to perform a write operation or a read operation.

A plurality of memory cells M are provided at a predetermined intersection between a word line WL and a data line DL, and are arranged in plurality in each well region. And the memory cell M is
A plurality of cells are arranged in a matrix to form a memory cell array.

Vss is a reference voltage (for example, 0 [V] or floating state or the same potential as the well during write operation) terminal, and is connected to the source region of the memory cell M.

X decoder 1. Y decoder 2. The well region voltage control circuit 3 constitutes a peripheral circuit of the FAMO 5.

Next, the specific structure of this embodiment will be explained.

FIG. 2 shows a FAMO for explaining one embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of memory cell No. 3;

In FIG. 2, reference numeral 4 denotes an n-type semiconductor substrate made of single-crystal silicon, and is used to constitute the FAMO 8.

A plurality of p-type well regions 5 are provided on the main surface of the semiconductor substrate 4 in a region where a plurality of memory cells are arranged. This well region 5 is for configuring a field effect transistor serving as a memory cell. A predetermined voltage is applied to the well region 5 by the well region voltage control circuit 3, and is used for writing or reading information.

A field insulating film 6 is provided mainly on the main surface of the semiconductor substrate 4 between regions where semiconductor elements are formed and on the main surface of the well region S. The field insulating film 6 is for electrically dividing 1171 between semiconductor elements. 67 is a P-type channel stopper region, which is provided on the main surface of the well region 5 under the field insulating film 6. This channel stopper region 7 is for further electrically isolating semiconductor elements.

Reference numeral 8 denotes an insulating film, which is provided on the upper main surface of the semiconductor substrate 4 and the upper main surface of the well region 5 in the region where semiconductor elements are formed. The insulating film 8 is mainly used to constitute a gate insulating film of a field effect transistor.

Reference numeral 9 denotes a conductive layer, which is provided on a predetermined portion of the insulating film 8. This conductive layer 9 serves as a floating gate electrode of a memory cell.

IO is an insulating film, and is provided at an intervening portion between a conductive layer 9 serving as a floating gate electrode and a control gate X11 pole to be described later. Specifically, the insulating film 1o is composed of a silicon oxide film 10A having a stoichiometric composition, and a silicon oxide film 10B having a silicon oxide film with a larger amount of silicon than the stoichiometric composition provided on top of the silicon oxide film 10A. In addition, the insulating film 1o
Alternatively, a plurality of silicon oxide films having a stoichiometric composition and a silicon oxide film having a silicon content larger than the stoichiometric composition may be sequentially stacked to form a plurality of layers.

This insulating film 10 has electrical characteristics such that electrons can be injected from the control gate electrode to the floating gate electrode (conductive layer 9) and vice versa (unidirectional electron injection). For a detailed explanation of this electrical characteristic, see D.

, T , DiM+xriia and D
, W. Dong, “HiBl+ curr.
ent-inject;ion inl;o SiS1
02fro Si rich SiO2 film
s and excrimenLaLa ρ
ρ1il2;il,1ons”,1,A
ppl, Pbys, 51(5), May 1! ]8
0 p2722-p2735.

11 is a conductive layer, and a plurality of conductive layers 9. '; established in the department.

A plurality of them are provided in the Y direction. The conductor II1 layer 11 is
The area where the semiconductor element is formed, that is, the conductive layer 9, constitutes the electrodes of the memory cell, and the other portion constitutes the word line WL.7 This conductive layer 11 is an insulating film 10 in a write operation.
Electrons serving as information are injected into the conductive layer 9 through the conductive layer 9.

Reference numeral 12 denotes an insulating film, which is provided to cover the conductive WI9.10. This insulating film 12 mainly consists of a conductive layer 9
This is to improve the retention characteristics of electrons, which become the information injected into the .

Reference numeral 13 denotes an RL type semiconductor region, which is located on both sides of conductive layers 19 and 11, and a source region (described later) is provided in the main part of the well region 5 between the train region and the channel region. . This semiconductor region 13 is.

In the read operation, the generation of hot carriers is suppressed,
L' (This is to prevent GF inclusion.

Reference numeral 14 denotes an insulating film, and an insulating film 12f! is formed on both sides of the conductive layers 9 and 11. : Provided through. This insulating layer 14 is for forming the semiconductor region 13. In addition,
The insulating film 14 may be removed during an intermediate manufacturing process and may not exist when the FAMOS is completed.

Reference numeral 15 denotes an Ω1 type semiconductor region, which is provided in the main part of the well region 5 on both sides of the insulating film 14 in the region where the semiconductor element is formed. This semiconductor region 15 is used as a substantial source region, a substantial drain region, or a ground line (not shown, but a wiring connected to the terminal Vss in FIG. 1), and is mainly used for memory cells. This is for constructing a field effect 1 field effect transistor. Semiconductor region 1 that becomes a substantial source region or drain region
5 is electrically connected to the semiconductor region 13.

A FAMOS memory cell M, that is, a field effect transistor, mainly includes a well region 5, a conductive layer 9 provided on the h portion of the well region 5 with an insulating film 8 interposed therebetween, and an insulating film 10 provided above the conductive layer 9. The conductive region WIll and a pair of semiconductor regions 13° and 15 are provided.

Reference numeral 16 denotes an insulating film, which is provided so as to cover a semiconductor element such as a field effect transistor. Insulation 11'J1
Reference numeral 6 is mainly for electrically separating the conductive layer 11 and a conductive layer provided on a portion thereof.

Reference numeral 17 denotes a connection hole, which is provided by removing the insulating films 8 and 16 from two portions of the predetermined semiconductor regions 15, .

This connection hole 17 is for electrically connecting the semiconductor region 15 and a conductive layer provided on the insulating film 16.

18 is a conductive layer, and a connection hole 17t! : A plurality of conductive conductors 111 are electrically connected to a predetermined semiconductor region 15 through the insulating film 16 and extend in the Y direction so as to intersect with the conductive W 111 in the X direction. This conductive layer 18 is connected to the data line DL.
It is for configuring.

Next, a specific manufacturing method of this example will be explained.

3 to 6 are sectional views of main parts of a FAMOS memory cell in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.

First, an n-type semiconductor substrate 4 made of single crystal silicon is prepared. Then, a p-type well region 5 is formed on the main surface of the semiconductor substrate 4, which will be a field-effect transistor forming region that will become a memory cell.

After this, a field insulating film 6 is formed on the semiconductor substrate 4 and the main surface of the well region 5 between the semiconductor elements, and in substantially the same step, a p-type channel stopper is formed on the main surface of the well region 5 below the field insulating film 6. Region 7 is formed.

Then, as shown in FIG. 3, it mainly becomes a memory cell. Field Effect 1 - An insulating film 8 is formed on the semiconductor substrate 4 (not shown) and the upper main surface of the well region 5 to serve as a gate insulating film of the transistor.

This insulating film 8 is made of, for example, silicon oxide formed by thermal oxidation technology, and has a thickness of 300 to 350 angstroms (hereinafter referred to as [A]) 1 F! Form in degrees.

After the process shown in FIG. 3, impurities are introduced into the main surface of the well region S through the insulating film 8 (not shown), mainly to form the first threshold voltage of the field effect transistor that becomes the memory cell. After that, a conductive Jiff 9A is formed on the insulating film 8 to form a floating gate electrode.

This conductive layer 9A is made of a polycrystalline silicon film formed by chemical vapor deposition (hereinafter referred to as "CvD") into which phosphorus is introduced.

Thereafter, insulating films 10A and 10B are sequentially stacked on top of conductive layer 9A to form insulating film 10.

The insulating film 10A is made of silicon oxide with a stoichiometric composition by CVD technology or thermal oxidation technology, and the film thickness is 100~
Formed with approximately 300 [A1].

The absolute 8 film 10B uses a silicon oxide film whose silicon content is larger than the stoichiometric composition obtained by CVD technology, and the film thickness is increased to 5.
Form a diameter of about 0 to 200 [A]. Specifically, 900
It is formed according to the following reaction using a CVD technique using SiH4 and N20 gas at a high temperature of about ['C] and a low pressure of about 1.0[sirl].

SiH4+2N20+SiO2+2N2+284 By changing the flow rate ratio of S x H4 and N20, a silicon oxide film with a large amount of silicon can be obtained.

Furthermore, 5iHz Cα and C○2 gas may be used.

Thereafter, a conductive layer is formed on the insulating film 10 to form a control gate electrode. This conductive layer is
A polycrystalline silicon film made by the D technology into which phosphorus is introduced is used.

and to form floating gate electrodes and control gate electrodes of memory cells.

The conductive layer 9 and the conductive layer formed thereon are patterned to form a conductive layer 9.11.

After this, an insulating film 12 is formed to cover the conductive layer N9.11.

Then, as shown in FIG. 5, an n-type semiconductor region 13 is formed on the main surface of the well region 5 through the insulating film 8 on both sides of the conductive layer 9.11. This semiconductor region 13 is provided with, for example, an I
XIO'"~IXl01" [at, oms/c+n
It may be formed by an ion implantation technique using arsenic ions of about 100 mL and an energy of about 80 [KeV].

After the process shown in FIG.
．． An insulating film 14 is formed on 11. This insulating film 14 is formed, for example, by forming a silicon oxide film over the entire surface using CVD technology, and then applying anisotropic etching technology.

Then, mainly using the insulating film 14 as a mask for introducing impurities, an n+ type semiconductor region 15 is formed on the main surface of the well region 5 through the insulating film 8 on both sides of the conductive layers 9 and 11. This semiconductor region 15 is, for example, I
It may be formed by an ion implantation technique using arsenic ions of about I Xl01'[atoms/cm'' and an energy of about 80 [KeV].

After the step shown in FIG. 6, an insulating film 16 is formed.

Then, the insulating film 16 above the predetermined semiconductor region 15 is removed to form a connection hole 17.

Thereafter, as shown in FIG. 2, the data line D is electrically connected to the semiconductor region 15 through the connection hole 17.
A conductive layer 18 is formed.

By performing these series of manufacturing steps, the F of this example
AMO8 is completed. Also, after this.

Even if a protective film or other treatment process is applied! stomach.

Next, the information writing and reading operations of this embodiment will be briefly explained with reference to FIGS. 1 and 2.

First, the write operation procedure will be explained.

A positive voltage (for example, +25 [V]) is applied to the well region 5 by the well region voltage control circuit 3 .

A negative voltage (for example, 0 [V]) is applied by the X decoder 1 to the conductive layer 11 serving as a control gate electrode. By setting such bias conditions, electrons are injected from the conductive layer 11 into the conductive layer 9 which becomes the floating gate electrode. At this time, from the conductive layer 9 to the conductive layer 11
Since the number of holes injected into the conductive layer 9 is very small compared to the number of electrons, this is substantially the same as electrons being injected into the conductive layer 9, and the conductive layer 9 becomes negatively charged. As a result, the first threshold voltage of the field effect transistor can be increased to the second threshold voltage, and an information write operation is performed.

At this time, the potentials of the source region and the drain region may be set to the same potential as that of the well or to a floating state.

Next, the read operation will be explained.

The well region voltage control circuit 3 applies a negative voltage (for example, O[V]) to the well region 5, and the X decoder 1 and Y decoder 2 apply a positive voltage to the conductive layer 11 and the semiconductor region 13.15 which becomes the drain region. Voltage (e.g.
r, V] ) is applied. In this state,
A field effect transistor having a first threshold voltage is
A channel current flows, and a field effect transistor having a second threshold voltage does not have a channel current. As a result, a read operation is performed to read the information of re O++, 1''.

That is, by providing the insulating film 10, the conductive layer 11
A banding operation can be performed by unidirectionally injecting electrons from the conductive layer 9 into the conductive layer 9. Therefore, it is possible to independently set the electrical characteristics of the write operation regardless of the read operation, so that it is possible to optimize them, for example, to improve the write efficiency.

Furthermore, by providing the semiconductor region 13.

Since the generation of hot carriers can be reduced,
Erroneous writing can be suppressed. As a result, the channel current can be increased, so that the read efficiency in the read operation can be improved and the speed of the FAMO 5 can be increased.6 Therefore, similarly to the write operation described above, regardless of the write operation.

Since the electrical characteristics of the read operation can be set,
It is possible to quantify it.

[Effects] As explained above, according to the novel technical means disclosed in this application, the following effects can be obtained.

(1) By providing a silicon oxide film with a stoichiometric composition and a silicon oxide film with a higher silicon content than the stoichiometric composition between the floating gate electrode and the control gate electrode, unidirectional electron Since injection can be performed, a write operation can be performed in which information is written from the control gate electrode to the bloating gate electrode.

(2) According to (1) above, the electrical characteristics of the write operation can be set independently from the read operation, so
This can be optimized.

(3) According to (1) above, the electrical characteristics of the read operation can be set independently from the write operation, so
This can be optimized.

(4) According to (1) above, since no channel current is required for write operation, current consumption can be reduced.

(5) The generation of hot carriers can be reduced by providing a low concentration semiconductor region of the same conductivity type as the source or drain region between the source or drain region and channel region of the field effect transistor. Therefore, erroneous writing in read operations can be suppressed.

(6) According to (5) above, fluctuations in the potential of the semiconductor substrate or well region can be reduced.

Latch-up due to parasitic bipolar transistors can be prevented.

(7) According to the above (5), erroneous writing can be prevented and the channel current can be increased, so that the read operation can be made faster.

(8) According to (5) and (6) above, the electrical reliability of FAMO3 can be improved.6 The invention made by the present inventor has been specifically explained in the above embodiments, The present invention is.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

For example, in the above embodiment, a field effect transistor serving as a memory cell is formed in a well region, but a single crystal silicon layer is provided on a semiconductor substrate or on the semiconductor substrate, and a single crystal silicon layer is formed on the main surface of the semiconductor substrate or It may be provided on the main surface of.

Further, in the above embodiment, an example was described in which a silicon oxide film with a stoichiometric composition and a silicon oxide film with a larger amount of silicon than the stoichiometric composition were formed by CVD technology.
A silicon oxide film having a stoichiometric composition may be formed by CVD technology, and silicon may be introduced into the upper layer by ion implantation technology to form a silicon oxide film having a larger amount of silicon than the stoichiometric composition.

[Brief explanation of the drawing]

FIG. 1 shows a FAMO for explaining one embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a memory cell array of No. 8, and FIG. 2 is a sectional view of a main part showing a memory cell of FAMO 3 for explaining one embodiment of the present invention. FIGS. 3 to 6 are cross-sectional views of essential parts showing a FAM*S memory cell in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention. In the figure, 1...X decoder, 2...Y decoder, 3...
...Well region potential control circuit, 4...Semiconductor substrate, 5
...Well region, 6...Field insulating film, 7...
・Channel stopper area, 8.10.12.14.16
...Insulating film, 9,11.18...Conductive layer, 10A.
... Silicon oxide film with stoichiometric composition, IOB... Silicon oxide IIi with a larger amount of silicon than the stoichiometric composition,
13°15...Semiconductor region, 17...Connection hole. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a field effect transistor constituted by a floating gate electrode and a control gate electrode provided above the floating gate electrode with an insulating film interposed therebetween, 1. A semiconductor integrated circuit device, wherein the insulating film is formed by sequentially stacking a silicon oxide film having a stoichiometric composition and a silicon oxide film having a higher silicon content than the stoichiometric composition. 2. The intervening insulating film is formed by sequentially stacking a plurality of layers of a silicon oxide film having a stoichiometric composition and a silicon oxide film having a larger amount of silicon than the stoichiometric composition. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor according to claim 1 or 2, wherein the field effect transistor is formed in a well region of a second conductivity type provided in a semiconductor substrate of a first conductivity type. Integrated circuit device. 4. The field effect transistor has a first conductivity type that is the same conductivity type as the source region or drain region, and has a first conductivity type that is the same conductivity type as the source region or drain region, and 4. The semiconductor integrated circuit device according to claim 3, further comprising a semiconductor region having an impurity concentration lower than that of the semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to each of claims 1 to 4, wherein the field effect transistor constitutes a memory cell of an ultraviolet erasable nonvolatile storage device.